ISL8023AIRTAJZ-T7A Intersil, ISL8023AIRTAJZ-T7A Datasheet - Page 18

• Manufacturer Part Number: ISL8023AIRTAJZ-T7A
• Description: ISL8023 Series 2.7 - 5.5 V 3 A 4 Mhz Buck Regulator - TQFN-16
• Manufacturer: Intersil

Figure 43 shows the type II compensator and its transfer function
is expressed as Equation 14:
where
Compensator design goal:
High DC gain
Loop bandwidth f
Gain margin: >10dB
Phase margin: 40°
The compensator design procedure is as follows:
Put compensator zero
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower. An
optional zero can boost the phase margin.
R
Put compensator zero
The loop gain T
Therefore, the compensator resistance R
Equation 15.
A
ω
R
2
v
cz1
6
( )
and C
S
=
=
=
,
2πf
--------------------------------- -
R2
GM V
R3
-------------- -
R
v ˆ
---------------- -
3
comp
c
v ˆ
6
1
.
V
FB
C
⋅
o
6
Vo
Vo
C
,
FB
=
o
v
FIGURE 43. TYPE II COMPENSATOR
ω
R
(S) at crossover frequency of f
-------------------- -
C
cz2
c
t
6
:
C3
GM
+
V REF
V REF
V FB
V FB
⎛
⎝
=
C
1
-- - to
4
ω
ω
7
-------------- -
R
cz1
cz2
2
----- -
10
1
⎛
⎝
---------------------------------------------------------
1
C
1
-
-
+
+
3
⎞ f
⎠
=
=
+
,
GM
s
ω
(
(
18
------------ -
ω
S 1
1to3
5to8
cp
cz1
S
⎛
⎝
=
⎞ 1
⎠
+
)
)
⎛
⎝
---------------------- -
R
C
--------- -
ω
-------------- -
R
-------------- -
R
6
S
R6
6
cp
o
2
C6
1
1
+
C
C
C
V COMP
V COMP
+
⎞
⎠
------------ -
ω
6
o
3
C
6
C
S
cz2
7
is determined by
7
ω
⎞
⎠
CZ2
c
C7
has unity gain.
is a zero due to
ISL8023, ISL8024
(EQ. 14)
(EQ. 15)
where GM is the sum of the trans-conductance, g
voltage error amplifier in each phase. Compensator capacitor C6
is then given by Equation 16.
Example: V
C
V
compensator resistance R
Put the compensator zero at 8kHz, and put the compensator pole
at either half of switching frequency or ESR zero. We choose
500kHz here, then the compensator capacitors are:
capacitance from V
Figure 44 shows the simulated voltage loop gain. It is shown that
it has 90kHz loop bandwidth with 70° phase margin and 10dB
gain margin.
C
C
FB
o
6
6
= 2X22µF/3mΩ, L = 1µH, GM = 150µs, R
= 220pF, C
=
= 0.6V, S
-15
-30
60
45
30
15
180
150
120
90
60
30
0
-------------------- - C
R
100
0
100
6
ω
1
cz1
IN
e
= 5V, V
,
= 440mV/µs, S
7
FIGURE 44. SIMULATED LOOP GAIN
= 3pF (There is approximately 3pF parasitic
7
=
COMP
1k
o
------------------------ -
2πR
1k
= 1.8V, I
1
6
to GND; Therefore, C
f
6
esr
= 100kΩ.
n
o
= 6.4×10
= 4A, f
f (fi)
10k
f (fi)
10k
s
= 1MHz,
5
V/s, f
t
= 0.20V/A,
7
100k
100k
c
optional).
m
= 100kHz, then
, of the
May 17, 2012
FN7812.2
(EQ. 16)
1M
1M