ISL8023AIRTAJZ-T7A Intersil, ISL8023AIRTAJZ-T7A Datasheet - Page 3

• Manufacturer Part Number: ISL8023AIRTAJZ-T7A
• Description: ISL8023 Series 2.7 - 5.5 V 3 A 4 Mhz Buck Regulator - TQFN-16
• Manufacturer: Intersil

Pin Configuration
Pin Descriptions
PIN NUMBER
Exposed Pad
13, 14, 15
11, 12
1, 16
8, 9
10
2
3
4
5
6
7
COMP, FB
SYMBOL
PHASE
SGND
PGND
SYNC
VDD
VIN
PG
EN
SS
3
FS
-
SYNC
VDD
VIN
PG
Input supply voltage. Connect two 22µF ceramic capacitors to power ground.
Input supply voltage for the logic. Connect VIN PIN.
Power-good is an open-drain output. Use 10kΩ to 100kΩ pull-up resistor connecting between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms upon output reached within regulation.
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case
of SYNIN pin float.
Regulator enable pin. Enable the output when driven to high. Shut down the chip and discharge output
capacitor when driven to low. There is an internal 1MΩ pull-down resistor to prevent an undefined logic
state in case of EN pin float.
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
and configured for internal compensation if FS is connected to VIN.
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor from
SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
The feedback network of the regulator, VFB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if FS resistor is used. Otherwise COMP is disconnected
thru a MOSFET for internal compensation. Recommend connecting COMP to SGND in internal
compensation mode. The output voltage is set by an external resistor divider connected to VFB. With
a properly selected divider, the output voltage can be set to any voltage between the power rail
(reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a
typical application. Additional external network across COMP and SGND might be required to improve
the loop compensation of the amplifier operation.
In addition, the regulator power-good and undervoltage protection circuitry use VFB to monitor the
regulator output voltage.
Signal ground.
Power ground.
Switching node connection. Connect to one terminal of the inductor.
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as
much vias as possible under the pad connecting to SGND plane for optimal thermal performance.
1
2
3
4
ISL8023, ISL8024
16
5
ISL8023, ISL8024
(16 LD TQFN)
TOP VIEW
15
6
14
7
13
8
12
DESCRIPTION
10
11
9
PGND
PGND
SGND
FB
May 17, 2012
FN7812.2