WT11i-E-AI4 Bluegiga Technologies, WT11i-E-AI4 Datasheet - Page 29

• Manufacturer Part Number: WT11i-E-AI4
• Description: Bluetooth / 802.15.1 Modules WT11i Class1 2.1+EDR uFL Conn iWRAP 4
• Manufacturer: Bluegiga Technologies

Specifications of WT11i-E-AI4

• Rohs: yes
• Class: 1
• Sensitivity: - 83 dBm
• Operating Supply Voltage: 3.3 V
• Interface Type: UART, USB
• Antenna Connector Type: Chip
• Maximum Operating Temperature: + 85 C
• Dimensions: 35.75 mm x 14.5 mm x 2.6 mm
• Mounting Style: SMD/SMT

MASTER CLK RATE
48M PCM CLK GEN
SAMPLE_FORMAT
SYNC SUPPRESS
SHORT SYNC EN
SIGN EXTENDED
RISING EDGE EN
SLAVE MODE EN
TX TRISTATE EN
SYNC LIMIT
LONG LENGTH
CNT RATE
CNT LIMIT
LSB FIRST EN
GCI MODE EN
TX TRISTATE
ACTIVE SLOT
Name
MUTE EN
SYNC EN
Name
EN
EN
EN
-
-
-
Bit position
Bit position
Table 13: PSKEY_PCM_LOW_JITTER_CONFIG Description
[23:16]
[31:24]
[20:16]
[22:21]
[26:23]
[28:27]
[12:0]
10
11
12
0
1
2
3
4
5
6
7
8
9
Table 12: PSKEY_PCM_CONFIG32 description
0 enables PCM_SYNC output when master, 1 suppresses PCM_SYNC
in the last bit of an active slot, assuming the next slot is also not active.
selected with 3-bit voice sample, the 3 padding bits are the audio gain
0 sets PCM_CLK and PCM_SYNC generation via DDS from internal 4
whilst keeping PCM_CLK running. Some CODECS utilize this to enter
Selects 128 (0b01), 256 (0b00), 512 (0b10) kHz PCM_CLK frequency
0 drives PCM_OUT continuously, 1 tri-states PCM_OUT immediately
0 tristates PCM_OUT immediately after the falling edge of PCM_CLK
0 sets PCM_SYNC length to 8 PCM_CLK cycles and 1 sets length to
0 transmits and receives voice samples MSB first, 1 uses LSB first.
PCM_SYNC. 1 selects Slave mode requiring externally generated
Selects between 13 (0b00), 16 (0b01), 8 (0b10) bit sample with 16
0 selects Master mode with internal generation of PCM_CLK and
0 selects long frame sync (rising edge indicates start of frame), 1
0 selects padding of 8 or 13-bit voice sample into a 16- bit slot by
Bluegiga Technologies Oy
after the falling edge of PCM_CLK in the last bit of an active slot,
inserting extra LSBs, 1 selects sign extension. When padding is
16 PCM_CLK cycles. Only applies for long frame sync and with
selects short frame sync (falling edge indicates start of frame).
MHz clock, as for BlueCore4-External. 1 sets PCM_CLK and
PCM_SYNC generation via DDS from internal 48 MHz clock.
when master and 48M_PCM_CLK_GEN_EN (bit 11) is low.
cycle slot duration 8 (0b11) bit sample 8 cycle slot duration.
1 tristates PCM_OUT after the rising edge of PCM_CLK.
setting; with 8-bit samples the 8 padding bits are zeroes.
PCM_CLK and PCM_SYNC. This should be set to 1 if
Sets PCM_SYNC division relative to PCM_CLK.
48M_PCM_CLK_GEN_EN (bit 11) is set.
Default is 0001. Ignored by firmaware
assuming the next slot is not active.
48M_PCM_CLK_GEN_EN set to 1.
Sets PCM_CLK counter limit
1 forces PCM_OUT to 0.
Sets PCM_CLK count rate.
1 enables GCI mode.
a low power state.
Set to 0b00000.
Description
Description
Set to 0
Set to 0
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