PCF2127AT/2Y NXP Semiconductors, PCF2127AT/2Y Datasheet
PCF2127AT/2Y
Specifications of PCF2127AT/2Y
Related parts for PCF2127AT/2Y
PCF2127AT/2Y Summary of contents
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PCF2127AT Integrated RTC, TCXO and quartz crystal Rev. 5 — 28 January 2013 1. General description The PCF2127AT Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal optimized for very high accuracy and very low power consumption. ...
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... NXP Semiconductors Clock operating voltage: 1 4.2 V Low supply current: typical 0.65 3. Applications Electronic metering for electricity, water, and gas Precision timekeeping Access to accurate time of the day GPS equipment to reduce time to first fix Applications that require an accurate process timing ...
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... NXP Semiconductors 6. Block diagram CLKOUT BBS V DD BATTERY BACK UP V SWITCH-OVER BAT CIRCUITRY V SS OSCILLATOR MONITOR RST INTERFACE SDA/CE SERIAL BUS SDO INTERFACE SDI SELECTOR SCL IFS INTERFACE TS PFI 1.25 V (internal) PFO Fig 1. Block diagram of PCF2127AT PCF2127AT Product data sheet TCXO OSCI 32 ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. 7.2 Pin description Table 4. Symbol SCL SDI SDO SDA/CE IFS TS CLKOUT V SS n.c. TEST PFO PFI RST INT BBS V BAT V DD PCF2127AT Product data sheet SCL 1 SDI 2 SDO 3 4 SDA/CE IFS CLKOUT n.c. 10 n.c. Top view. For mechanical details, see ...
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... NXP Semiconductors 8. Functional description The PCF2127AT is a Real Time Clock (RTC) and calendar with an on-chip Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal integrated into the same package (see Address and data are transferred by a selectable 400 kHz Fast-mode I SPI-bus with separate data input and output (see SPI-bus is 6 ...
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... NXP Semiconductors • The register at address 0Fh defines the temperature measurement period and the clock out mode. The temperature measurement can be selected from every 4 minutes (default) down to every 30 seconds (see 32.768 kHz (default) down for use as system clock, microcontroller clock, and so on, can be chosen (see • ...
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... NXP Semiconductors Table 5. Register overview Bit positions labeled as - are not implemented and will return a 0 when read. Bit T must always be written with logic 0. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address Register name Bit 7 Control registers 00h Control_1 ...
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... NXP Semiconductors Table 5. Register overview …continued Bit positions labeled as - are not implemented and will return a 0 when read. Bit T must always be written with logic 0. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address Register name Bit 7 RAM registers 1Ah ...
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... NXP Semiconductors 8.2 Control registers The first 3 registers of the PCF2127AT, with the addresses 00h, 01h, and 02h, are used as control registers. 8.2.1 Register Control_1 Table 6. Bit [1] Default value. [2] When writing to the register this bit always has to be set logic 0. ...
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... NXP Semiconductors 8.2.2 Register Control_2 Table 7. Bit [1] Default value. PCF2127AT Product data sheet Control_2 - control and status register 2 (address 01h) bit description Symbol Value Description [1] MSF 0 no minute or second interrupt generated 1 flag set when minute or second interrupt generated; ...
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... NXP Semiconductors 8.2.3 Register Control_3 Table 8. Bit PWRMNG[2: [1] Values see [2] Default value. PCF2127AT Product data sheet Control_3 - control and status register 3 (address 02h) bit description Symbol Value Description [1] control of the battery switch-over, battery low detection, and extra power fail detection ...
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... NXP Semiconductors 8.3 Register CLKOUT_ctl Table 9. Bit Symbol TCR[1: COF[2:0] 8.3.1 Temperature compensated crystal oscillator The frequency of tuning fork quartz crystal oscillators is temperature-dependent. In the PCF2127AT, the frequency deviation caused by temperature variation is corrected by adjusting the load capacitance of the crystal oscillator. ...
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... NXP Semiconductors Table 11. COF[2:0] [2][3] 000 001 010 011 100 101 110 111 [1] Duty cycle definition: % HIGH-level time : % LOW-level time. [2] Default value. [3] The specified accuracy of the RTC can be only achieved with CLKOUT frequencies not equal to 32.768 kHz or if CLKOUT is disabled. PCF2127AT Product data sheet ...
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... NXP Semiconductors 8.4 Register Aging_offset Table 12. Bit Symbol AO[3:0] 8.4.1 Crystal aging correction The PCF2127AT has an offset register Aging_offset to correct the crystal aging effects The accuracy of the frequency of a quartz crystal depends on its aging. The aging offset adds an adjustment, positive or negative, in the temperature compensation circuit which allows correcting the aging effect ...
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... NXP Semiconductors 8.5 General purpose 512 bytes static RAM The PCF2127AT contains a general purpose 512 bytes static RAM. This integrated SRAM is battery backed and can therefore be used to store data which is essential for the application to survive a power outage. 9 bits, RA[8:0], define the RAM address pointer in registers RAM_addr_MSB and RAM_addr_LSB ...
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... NXP Semiconductors 8.5.5 Operation examples 8.5.5.1 Writing to the RAM 1. Set RAM address: – Select register RAM_addr_MSB (send address 1Ah). – Set value for bit RA8 (data byte of register 1Ah). Note: register address will be incremented automatically to 1Bh. – Set value for array RA[7:0] (data byte of register 1Bh). ...
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... NXP Semiconductors 8.6 Power management functions The PCF2127AT has two power supply pins and one power output pin: • • V BAT • BBS - battery backed output voltage pin (equal to the internal power supply) The PCF2127AT has three power management functions implemented: • ...
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... NXP Semiconductors 8.6.1 Battery switch-over function The PCF2127AT has a backup battery switch-over circuit which monitors the main power supply V backup battery. One of two operation modes can be selected: • Standard mode: the power failure condition happens when th(sw)bat switch-over in standard mode works only for V • ...
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... NXP Semiconductors 8.6.1.1 Standard mode If V > < th(sw)bat (= 2 Fig 4. PCF2127AT Product data sheet OR V > the internal power supply is V BAT DD th(sw)bat AND V < the internal power supply is V BAT DD th(sw)bat backup battery operation BBS ...
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... NXP Semiconductors 8.6.1.2 Direct switching mode If V > < The direct switching mode is useful in systems where V This mode is not recommended if the 3 compared to the standard mode because the monitoring of V performed th(sw)bat (= 2 Fig 5. 8.6.1.3 Battery switch-over disabled: only one power supply (V When the battery switch-over function is disabled: • ...
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... NXP Semiconductors 8.6.1.4 Battery switch-over architecture The architecture of the battery switch-over circuit is shown in Fig 6. The internal power supply (available on pin BBS) is equal to V assured that there are decoupling capacitors on the pins V 8.6.2 Battery backup supply The V BBS on the selected battery switch-over function mode: Table 19 ...
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... NXP Semiconductors V BBS (mV) Fig 7. 8.6.3 Battery low detection function The PCF2127AT has a battery low detection circuit which monitors the status of the battery V When V (register Control_3) is set to indicate that the battery is low and that it must be replaced. Monitoring of the battery voltage also occurs during battery operation. ...
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... NXP Semiconductors th(bat)low (= 2.5 V) Fig 8. 8.6.4 Extra power fail detection function The PCF2127AT has an extra power fail detection circuit which compares the voltage at the power fail input pin PFI to an internal reference voltage equal to 1. < 1.25 V, the power fail output PFO is driven LOW. PFO is an open-drain, active PFI LOW output which requires an external pull-up resistor in any application ...
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... NXP Semiconductors V th uvp V th(uvp) below the minimum operating voltage of the system, in order to allow the microcontroller to perform early backup operations. If the extra power fail detection function is not used, pin PFI must be connected to V pin PFO must be left open circuit. 8.6.4.1 Extra power fail detection when the battery switch over function is enabled • ...
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... NXP Semiconductors th(uvp) V th(sw)bat (= 2 comparator enabled PF0 Fig 11. PFO signal behavior when battery switch-over is enabled in direct switching 8.6.4.2 Extra power fail detection when the battery switch-over function is disabled If the battery switch-over function is disabled and the power fail comparator is enabled, ...
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... NXP Semiconductors 8.7 Oscillator stop detection function The PCF2127AT has an on-chip oscillator detection circuit which monitors the status of the oscillation: whenever the oscillation stops, a reset occurs and the oscillator stop flag OSF (in register Seconds) is set logic 1. • Power-on: a. The oscillator is not running, the chip is in reset (pin RST is LOW and flag OSF is logic 1) ...
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... NXP Semiconductors 8.8 Reset function The PCF2127AT has a Power-On Reset (POR) and a Power-On Reset Override (PORO) function implemented. 8.8.1 Power-On Reset (POR) The POR is active whenever the oscillator is stopped. The oscillator is also considered to be stopped during the time between power-on and stable crystal resonance (see Figure 14) ...
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... NXP Semiconductors Fig 15. Power-On Reset (POR) system The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in SDA/CE reset override Fig 16. Power-On Reset Override (PORO) sequence, valid for both I Once the override mode is entered, the device is immediately released from the reset state and the set-up operation can commence ...
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... NXP Semiconductors 8.9 Time and date function Most of these registers are coded in the Binary Coded Decimal (BCD) format. 8.9.1 Register Seconds Table 20. Bit Symbol 7 OSF SECONDS [1] Start-up value. Table 21. Seconds value in decimal 8.9.2 Register Minutes Table 22. Bit Symbol ...
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... NXP Semiconductors 8.9.3 Register Hours Table 23. Bit Symbol hour mode 5 AMPM 4 HOURS hour mode HOURS [1] Hour mode is set by the bit 12_24 in register Control_1. 8.9.4 Register Days Table 24. Bit Symbol DAYS [1] If the year counter contains a value which is exactly divisible by 4, including the year 00, the RTC compensates for leap years by adding ...
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... NXP Semiconductors 8.9.6 Register Months Table 27. Bit Symbol MONTHS Table 28. Month January February March April May June July August September October November December 8.9.7 Register Years Table 29. Bit Symbol YEARS 8.9.8 Setting and reading the time Figure 17 During read/write operations, the time counting circuits (memory locations 03h through 09h) are blocked ...
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... NXP Semiconductors Fig 17. Data flow of the time function After this read/write access is completed, the time circuit is released again. Any pending request to increment the time counters that occurred during the read/write access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Fig 18 ...
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... NXP Semiconductors 8.10 Alarm function When one or more of the alarm bit fields are loaded with a valid second, minute, hour, day, or weekday and its corresponding alarm enable bit (AE_x) is logic 0, then that information is compared with the actual second, minute, hour, day, and weekday (see (1) Only when all enabled alarm settings are matching ...
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... NXP Semiconductors 8.10.2 Register Minute_alarm Table 31. Bit Symbol 7 AE_M MINUTE_ALARM [1] Default value. 8.10.3 Register Hour_alarm Table 32. Bit Symbol 7 AE_H hour mode 5 AMPM 4 HOUR_ALARM hour mode HOUR_ALARM [1] Default value. [2] Hour mode is set by the bit 12_24 in register Control_1. ...
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... NXP Semiconductors 8.10.5 Register Weekday_alarm Table 34. Bit Symbol 7 AE_W WEEKDAY_ALARM [1] Default value. 8.10.6 Alarm flag When all enabled comparisons first match, the alarm flag AF (register Control_2) is set. AF will remain set until cleared by command. Once AF has been cleared, it will only be set again when the time increments to match the alarm condition once more ...
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... NXP Semiconductors 8.11 Timer functions The PCF2127AT has two different timer functions, a watchdog timer and a countdown timer. The timers can be selected by using the control bits WD_CD[1:0] in the register Watchdg_tim_ctl. • The watchdog timer has four selectable source clocks. It can, for example, be used to ...
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... NXP Semiconductors 8.11.2 Register Watchdg_tim_val Table 36. Bit WATCHDG_TIM_VAL[7:0] Table 37. TF[1:0] Timer source 8.11.3 Watchdog timer function The watchdog timer function is enabled or disabled by the WD_CD[1:0] bits of the register Watchdg_tim_ctl (see The two bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or ...
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... NXP Semiconductors Remark: WDTF is read only and cannot be cleared by command. WDTF can be cleared by: • loading a value in register Watchdg_tim_val • reading of the register Control_2 Writing a logic 0 or logic 1 to WDTF has no effect. watchdog timer value WDTF Fig 21. WD_CD[1:0] = 10: watchdog activates an interrupt when timed out • ...
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... NXP Semiconductors Table 38. WD_CD[1:0] 11 8.11.4 Countdown timer function The countdown timer function is controlled by the WD_CD[1:0] bits in register Watchdg_tim_ctl (see The timer counts down from the software programmed 8 bit binary value n in register Watchdg_tim_val. When the counter reaches 1 • the countdown timer flag CDTF is set • ...
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... NXP Semiconductors If this mode is enabled and the countdown timer flag CDTF is set, an interrupt signal on INT will be generated. See controlled. When starting the countdown timer for the first time, only the first period will not have a fixed duration. The amount of inaccuracy for the first timer period will depend on the chosen source clock, see Table 39 ...
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... NXP Semiconductors Table 41. Register Control_2 The following tables show what instruction must be sent to clear the appropriate flag. Table 42. Register Control_2 [1] The bits labeled as - have to be rewritten with the previous values. Table 43. Register Control_2 [1] The bits labeled as - have to be rewritten with the previous values. ...
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... NXP Semiconductors 8.12 Timestamp function The PCF2127AT has an active LOW timestamp input pin TS, internally pulled with an on-chip pull-up resistor to the internal power supply of the device. It also has a timestamp detection circuit which can detect two different events: 1. Input on pin TS is driven to an intermediate level between power supply and ground. ...
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... NXP Semiconductors The TSF1 and TSF2 flags can be cleared by command; clearing both flags will clear the interrupt. Once TSF2 is cleared, it will only be set again when TS pin is driven to ground once again. 8.12.2 Timestamp mode The timestamp function has two different modes selected by the control bit TSM (timestamp mode) in register Timestp_ctl: • ...
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... NXP Semiconductors 8.12.3.4 Register Hour_timestp Table 49. Bit Symbol hour mode 5 AMPM 4 HOUR_TIMESTP hour mode HOUR_TIMESTP [1] Hour mode is set by the bit 12_24 in register Control_1. 8.12.3.5 Register Day_timestp Table 50. Bit Symbol DAY_TIMESTP 8.12.3.6 Register Mon_timestp Table 51 ...
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... NXP Semiconductors 8.12.4 Dependency between Battery switch-over and timestamp The timestamp function depends on the control bit BTSE in register Control_3: Table 53. BTSE [1] Default value. PCF2127AT Product data sheet Battery switch-over and timestamp Description [1] - the battery switch-over does not affect the timestamp registers ...
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... NXP Semiconductors 8.13 Interrupt output, INT SECONDS COUNTER MINUTES COUNTER from interface: clear MSF WD_CD[1: COUNTDOWN COUNTER from interface: clear CDTF WD_CD[1: WATCHDOG COUNTER MCU loading watchdog counter set alarm flag, AF from interface: clear AF set timestamp flag, TSFx from interface: clear TSFx ...
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... NXP Semiconductors • watchdog timer • alarm • timestamp • battery switch-over • battery low detection The control bit TI_TP (register Watchdg_tim_ctl) is used to configure whether the interrupts generated from the second/minute timer (flag MSF in register Control_2) and the countdown timer (flag CDTF in register Control_2) are pulsed signals or a permanently active signal ...
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... NXP Semiconductors INT when only MI enabled MSF when only MI enabled Fig 26. INT example for SI and MI when TI_TP is logic 1 Fig 27. INT example for SI and MI when TI_TP is logic 0 The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock and generates a pulse of 8 ...
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... NXP Semiconductors 8.13.3 INT pulse shortening The pulse generator for the countdown timer interrupt also uses an internal clock, but this time it is dependent on the selected source clock for the countdown timer and on the countdown value consequence, the width of the interrupt pulse varies (see Table 55) ...
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... NXP Semiconductors (1) Indicates normal duration of INT pulse. Fig 29. Example of shortening the INT pulse by clearing the CDTF flag 8.13.4 Watchdog timer interrupts The generation of interrupts from the watchdog timer is controlled using the WD_CD[1:0] bits (register Watchdg_tim_ctl). The interrupt is generated as an active signal which follows the status of the watchdog timer flag WDTF (register Control_2) ...
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... NXP Semiconductors 8.13.6 Timestamp interrupts Interrupt generation from the timestamp function is controlled using the TSIE bit (register Control_2). If TSIE is enabled, the INT pin follows the status of the flags TSFx. Clearing the flags TSFx immediately clears INT. No pulse generation is possible for timestamp interrupts. ...
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... NXP Semiconductors 8.14 External clock test mode A test mode is available which allows on-board testing. In this mode possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit EXT_TEST logic 1 (register Control_1). Then pin CLKOUT becomes an input. The test mode replaces the internal clock signal (64 Hz) with the signal applied to pin CLKOUT ...
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... NXP Semiconductors 8.15 STOP bit function The function of the STOP bit is to allow for accurate starting of the time circuits. STOP will cause the upper part of the prescaler (F are generated. The time circuits can then be set and will not increment until the STOP bit is released ...
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... NXP Semiconductors 32768 Hz F OSC Fig 31. STOP bit functional diagram Fig 32. STOP bit release timing PCF2127AT Product data sheet LOWER PRESCALER 128 Hz 16384 Hz 8192 Hz 4096 stop released All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 January 2013 ...
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... NXP Semiconductors 9. Interfaces The PCF2127AT has done by using the interface selection pin IFS (see Table 57. Pin IFS V DD SCL SDI SDO CE SCL 1 SDI 2 SDO 3 SDA/CE 4 IFS 5 PCF2127AT select the SPI-bus interface, pin IFS has to be connected to pin V ...
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... NXP Semiconductors 9.1 SPI-bus interface Data transfer to and from the device is made line SPI-bus (see lines for input and output are split. The data input and output line can be connected together to facilitate a bidirectional data bus (see whenever the chip enable line pin SDA/CE is inactive. ...
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... NXP Semiconductors Table 59. Bit R SCL SDI SDA/CE address xx counter In this example, the Seconds register is set to 45 seconds and the Minutes register to 10 minutes. Fig 36. SPI-bus write example R SCL SDI ...
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... NXP Semiconductors 2 9.2 I C-bus interface 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines are connected to a positive supply by a pull-up resistor. Data transfer is initiated only when the bus is not busy ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER RECEIVER Fig 40. System configuration 9.2.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver which is addressed must generate an acknowledge after the reception of each byte. • ...
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... NXP Semiconductors 2 9.2.5 I C-bus protocol After a start condition, a valid hardware address has to be sent to a PCF2127AT device. The appropriate I is shown in Table 60. Bit The R/W bit defines the direction of the following single or multiple byte data transfer (read is logic 1, write is logic 0). For the format and the timing of the START condition (S), the STOP condition (P), and the ...
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... NXP Semiconductors S P/S Fig 44. Bus protocol, writing to RAM PCF2127AT Product data sheet acknowledge from PCF2127AT slave address write bit acknowledge from PCF2127AT data byte 1Ah A acknowledge from PCF2127AT slave address write bit acknowledge from PCF2127AT ...
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... NXP Semiconductors S P/S P/S Fig 45. Bus protocol, reading from RAM PCF2127AT Product data sheet acknowledge from PCF2127AT slave address write bit acknowledge from PCF2127AT data byte 1Ah A acknowledge from PCF2127AT slave address write bit acknowledge ...
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... NXP Semiconductors 10. Internal circuitry Fig 46. Device diode protection diagram of PCF2127AT PCF2127AT Product data sheet SCL SDI SDO SDA/CE IFS TS CLKOUT V SS PCF2127AT All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 January 2013 PCF2127AT Integrated RTC, TCXO and quartz crystal ...
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... NXP Semiconductors 11. Limiting values Table 61. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol BAT P tot V ESD stg T amb [1] Pass level; Human Body Model (HBM) according to [2] Pass level; Charged-Device Model (CDM), according to [3] Pass level ...
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... NXP Semiconductors 12. Static characteristics Table 62. Static characteristics Symbol Parameter Supplies V supply voltage DD V battery supply voltage BAT V calibration supply voltage DD(cal) V low voltage low I supply current DD I battery leakage current L(bat) PCF2127AT Product data sheet = 40 C to +85 C, unless otherwise specified. ...
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... NXP Semiconductors Table 62. Static characteristics Symbol Parameter Power management V battery switch threshold th(sw)bat voltage V low battery threshold voltage th(bat)low V threshold voltage on pin PFI th(PFI) [4] Inputs V input voltage I V LOW-level input voltage IL V HIGH-level input voltage IH I input leakage current ...
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... NXP Semiconductors 12.1 Current consumption characteristics, typical Fig 47. I (μA) Fig 48. I PCF2127AT Product data sheet (mA 1.5 Typical value 0 pin SDA/ 1.6 1.2 0.8 0.4 0 −40 −20 0 CLKOUT disabled; PWRMNG[2:0] = 111; TSOFF = 1; TS input floating function of temperature DD All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors (μA) a. PWRMNG[2:0] = 111; TSOFF = 1; T (μA) b. PWRMNG[2:0] = 000; TSOFF = 0; T Fig 49. I PCF2127AT Product data sheet 2 1.6 1.2 0.8 0.4 0 1.8 2.2 2.6 4 3.2 2.4 1.6 0.8 0 1.8 2.2 2 function All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 January 2013 PCF2127AT Integrated RTC, TCXO and quartz crystal ...
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... NXP Semiconductors 12.2 Frequency characteristics Table 63. Frequency characteristics Symbol Parameter f output frequency o f/f frequency stability f /f relative crystal frequency variation crystal aging, first year; xtal xtal f/V frequency variation with voltage 1 ppm corresponds to a time deviation of 0.0864 seconds per day. ...
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... NXP Semiconductors 13. Dynamic characteristics 13.1 SPI-bus timing characteristics Table 64. SPI-bus characteristics operating supply voltage at ambient temperature and referenced to V Symbol Parameter Pin SCL f SCL clock frequency clk(SCL) t SCL time SCL t clock HIGH time clk(H) t clock LOW time ...
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... NXP Semiconductors CE t su(CE_N) SCL WRITE SDI R/W SA2 high-Z SDO READ SDI b7 high-Z SDO Fig 51. SPI-bus timing PCF2127AT Product data sheet t w(CE_N 80% 20% RA0 t(SDI-SDO) All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 January 2013 ...
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... NXP Semiconductors 2 13 interface timing characteristics Table 65. All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference and 70 % with an input voltage swing of V Symbol Parameter Pin SCL f SCL t LOW t HIGH Pin SDA/CE t SU;DAT t HD;DAT ...
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... NXP Semiconductors START PROTOCOL CONDITION (S) t SU;STA SCL t BUF SDA t HD;STA 2 Fig 52. I C-bus timing diagram; rise and fall times refer and 70 % 14. Application information For information about application configuration, see PCF2127AT Product data sheet BIT 7 BIT 6 MSB (A6) (A7 LOW ...
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... NXP Semiconductors 15. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors 16. Packing information 16.1 Carrier tape information Fig 54. Tape and reel details for PCF2127AT Table 66. Symbol Compartments Overall dimensions 17. Soldering For information about soldering, see PCF2127AT Product data sheet TOP VIEW direction of feed Original dimensions are in mm. ...
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... NXP Semiconductors 18. Footprint information solder lands occupied area Fig 55. Footprint information for reflow soldering of SO20 package PCF2127AT Product data sheet 13.40 0.60 (20×) 1.50 8.00 1.27 (18×) placement accuracy ± 0.25 Dimensions in mm All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 January 2013 PCF2127AT Integrated RTC, TCXO and quartz crystal 11 ...
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... NXP Semiconductors 19. Abbreviations Table 67. Acronym AM BCD CDM CMOS DC GPS HBM LSB MCU MSB PM POR PORO PPM RAM RC RTC SCL SDA SPI SRAM TCXO Xtal PCF2127AT Product data sheet Abbreviations Description Ante Meridiem Binary Coded Decimal Charged Device Model Complementary Metal-Oxide Semiconductor ...
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... NXP Semiconductors 20. References [1] AN10365 — Surface mount reflow soldering description [2] AN10853 — Handling precautions of ESD sensitive devices [3] AN10857 — Application and soldering information for PCF2127A and PCF2129A TCXO RTC [4] IEC 60134 — Rating systems for electronic tubes and valves and analogous ...
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... NXP Semiconductors 21. Revision history Table 68. Revision history Document ID Release date PCF2127AT v.5 20130128 • Modifications: Improved description of V PCF2127AT v.4 20121207 PCF2127AT v.3 20121004 PCF2127A v.2 20100507 PCF2127A v.1 20100121 PCF2127AT Product data sheet Data sheet status Product data sheet pin in Table 4 BAT Product data sheet ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... For sales office addresses, please send an email to: PCF2127AT Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Table 2. Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2 Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 Table 4. Pin description of SO20 (PCF2127AT Table 5. Register overview . . . . . . . . . . . . . . . . . . . . . . .7 Table 6. Control_1 - control and status register 1 (address 00h) bit description . . . . . . . . . . . . . . .9 Table 7. Control_2 - control and status register 2 (address 01h) bit description . . . . . . . . . . . . . .10 Table 8. ...
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... NXP Semiconductors 25. Figures Fig 1. Block diagram of PCF2127AT . . . . . . . . . . . . . . . .3 Fig 2. Pin configuration for SO20 (PCF2127AT Fig 3. Handling address registers . . . . . . . . . . . . . . . . . .5 Fig 4. Battery switch-over behavior in standard mode with bit BIE set logic 1 (enabled .19 Fig 5. Battery switch-over behavior in direct switching mode with bit BIE set logic 1 (enabled .20 Fig 6 ...
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... NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 5 8.1 Register overview . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 9 8.2.1 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 9 8.2.2 Register Control_2 . . . . . . . . . . . . . . . . . . . . . 10 8.2.3 Register Control_3 . . . . . . . . . . . . . . . . . . . . . 11 8.3 Register CLKOUT_ctl . . . . . . . . . . . . . . . . . . . 12 8 ...
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... NXP Semiconductors 8.14 External clock test mode . . . . . . . . . . . . . . . . 52 8.15 STOP bit function . . . . . . . . . . . . . . . . . . . . . . 53 9 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.1 SPI-bus interface . . . . . . . . . . . . . . . . . . . . . . 56 9.1.1 Data transmission . . . . . . . . . . . . . . . . . . . . . . 56 2 9.2 I C-bus interface 9.2.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2.2 START and STOP conditions . . . . . . . . . . . . . 58 9.2.3 System configuration . . . . . . . . . . . . . . . . . . . 58 9.2.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 59 2 9.2.5 I C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 60 10 Internal circuitry Limiting values Static characteristics 12.1 Current consumption characteristics, typical . 67 12 ...