STMPE812ABJR STMicroelectronics, STMPE812ABJR Datasheet - Page 24
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STMPE812ABJR
Manufacturer Part Number
STMPE812ABJR
Description
Touch Screen Converters & Controllers Touchscreen cntrlr S-Touch
Manufacturer
STMicroelectronics
Type
Resistive Touch Controllersr
Datasheet
1.STMPE812ABJR.pdf
(53 pages)
Specifications of STMPE812ABJR
Rohs
yes
Input Type
1 TSC
Data Rate
400 kbps
Resolution
12 bit
Interface Type
4-wire, I2C
Supply Voltage
1.65 V to 3.6 V
Supply Current
100 uA
Operating Temperature
- 40 C to + 85 C
Package / Case
CSP-12
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.65 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STMPE812ABJR
Manufacturer:
SMSC
Quantity:
154
Part Number:
STMPE812ABJR
Manufacturer:
ST
Quantity:
20 000
Interrupt system
ISR
Address:
Type:
Reset:
Description:
Note: Reading the Interrupt Enable Register also clears the ISR. It is recommended that no read operation on IER
24/53
TSC_ERR
7
0
to be executed during normal operation. IER should only be accessed during initialization.
TSC_RELEASE
In PEN_DOWN interrupt mode, this status register will still be updated with event interrupt
status data, and cleared on read. However no interrupt will be issued based on this status
register.
[7] TSC_ERR
[6] TSC_RELEASE:
[5] P2
[4] RESERVED
[3] P1
[2] P0
[1] TSC_DATA
[0] TSC_TOUCH
6
0
0x0A
R
0x00
ISR register monitors the status of the interruption from a particular interrupt source
to the host. Regardless whether the INT_EN bits are enabled, the ISR bits are still
updated.
Writing to this register has no effect. Reading the register clears any asserted bit
Implementation: A shadow register MUST be used to ensure that Read+Clear action
DOES NOT clear up any bit that is not READ.
Error encountered in coordinate calculation in TSC, or touch detect not valid after sampling
Release of touch is detected
Port 2 activity (GPIO)
Port 1 activity (GPIO/ADC/PWM)
Port 0 activity (GPIO)
Touch data available. In internal timer and host-read controlled mode, this bit can only
be cleared after the data has been read by the host. In ACQ mode, this bit is cleared after the
data or the ISR is read by the host.
Touch is detected.
(In PEN-DOWN interrupt mode, this bit is never cleared until pen is removed)
P2
5
0
RESERVED
4
0
Doc ID 18225 Rev 4
P1
3
0
P0
2
0
Interrupt status register
TSC_DATA
1
0
STMPE812A
TSC_TOUCH
0
0