SSTUB32865ET/G,518 NXP Semiconductors, SSTUB32865ET/G,518 Datasheet - Page 21

• Manufacturer Part Number: SSTUB32865ET/G,518
• Description: IC REG BUFFER 28BIT 160TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUB32865ET/G,518

• Logic Type: 1:2 Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-TFBGA
• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 2V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 160
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3542-2; 935281691518; SSTUB32865ET/G-T

NXP Semiconductors
SSTUB32865_3
Product data sheet
11.3 Error output load circuit and voltage measurement
V
All input pulses are supplied by generators having the following characteristics:
PRR
Fig 18. Load circuit, error output measurements
Fig 19. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
Fig 20. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect
DD
= 1.8 V
(1) C
10 MHz; Z
RESET input
to clock inputs
L
includes probe and jig capacitance.
0.1 V.
o
waveform 1
= 50 ; input slew rate = 1 V/ns
waveform 2
RESET
output
timing
inputs
Rev. 03 — 27 March 2007
output
LVCMOS
t
DUT
PLH
OUT
V
t
HL
0.5V
ICR
0.15 V
DD
1.8 V DDR2-800 registered buffer with parity
0.5V
DD
C
L
= 10 pF
V
ICR
(1)
20 %, unless otherwise specified.
V
DD
R
test point
002aaa500
L
002aaa502
= 1 k
SSTUB32865
002aaa501
V
V
V
V
0 V
V
0 V
DD
OL
i(p-p)
DD
OH
© NXP B.V. 2007. All rights reserved.
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