MAXQ615-F00+ Maxim Integrated, MAXQ615-F00+ Datasheet - Page 12
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MAXQ615-F00+
Manufacturer Part Number
MAXQ615-F00+
Description
16-bit Microcontrollers - MCU MICRO 16PIN
Manufacturer
Maxim Integrated
Datasheet
1.MAXQ615-F00.pdf
(20 pages)
Specifications of MAXQ615-F00+
Rohs
yes
Core
MAXQ20S
Processor Series
MAXQ615
Data Bus Width
16 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
48 KB
Data Ram Size
2 KB
Operating Supply Voltage
2.4 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TQFN-16
Mounting Style
SMD/SMT
Interface Type
I2C, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
12
Number Of Timers
3
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.4 V
Part # Aliases
90-M3900+F00
The general-purpose I/O pins have the following features:
• CMOS output drivers
• Schmitt trigger inputs
• Optional weak pullup to V
While the microcontroller is in a reset state, all port pins
become high impedance with input buffers and weak
pullups disabled, unless otherwise noted.
From a software perspective, each port appears as a
group of peripheral registers with unique addresses.
Special function pins can also be used as general-pur-
pose I/O pins when the special functions are disabled.
For a detailed description of the special functions avail-
able for each pin, refer to the user manual for this device.
The microcontroller provides three timers/counters that
support the following functions:
• 16-bit timer/counter
• 16-bit up/down autoreload
• Counter function of external pulse
• 16-bit timer with capture
• 16-bit timer with compare
• Input/output enhancements for pulse-width modulation
• Set/reset/toggle output state on comparator match
• Prescaler with 2n divider (for n = 0, 2, 4, 6, 8, 10)
The device provides two SPI ports. The SPI is an inter-
device bus protocol that provides fast, synchronous, full-
duplex communications between devices. The integrated
SPI interface acts as either an SPI master or slave device.
The master drives the synchronous clock and selects
which of several slaves is being addressed. Every SPI
peripheral consists of a single shift register and control
circuitry so that an addressed serial peripheral interface
SPI peripheral is simultaneously transmitting and receiv-
ing. The maximum SPI master transfer rate is Sysclk/2.
When operating as an SPI slave, the device can support
up to Sysclk/4 SPI transfer rate. Data can be transferred
Maxim Integrated
mode
Serial Peripheral Interface (SPI)
16-Bit Timers/Counters
General-Purpose I/O
Serial Peripherals
DD
when operating in input
16-Bit MAXQ Microcontroller with
as an 8-bit or 16-bit value, MSB first. In addition, the SPI
module supports configuration of the active SSEL state
through the slave active-select pin.
Four signals are used in SPI communication:
• SCLK: The synchronous clock used by all devices.
• MOSI: Master out-slave in. This is the main data line
• MISO: Master in-slave out. This is the main data line
• SSEL: This signal is unique to each slave. When
The microcontroller provides an internal I
slave for communication with a wide variety of other
I
tional bus using two bus lines—the serial data line (SDA)
and the serial clock line (SCL)—and a ground line. Both
the SDA and SDL lines must be driven as open-collector/
drain outputs. External resistors are required to pull the
lines to a logic-high state.
The device supports both the master and slave proto-
cols. In the master mode, the device has ownership of
the I
and STOP signals. This allows it to send data to a slave or
receive data from a slave as required. In slave mode, the
device relies on an externally generated clock to drive
SCL and responds to data and commands only when
requested by the I
The internal hardware multiplier supports high-speed
multiplications. The multiplier can complete a 16-bit x
16-bit multiply-and-accumulate/subtract operation in a
single cycle with the support of a 48-bit accumulator. The
multiplier is a fixed-point arithmetic unit. The operands
can be either signed or unsigned numbers, but the data
type must be defined by the application software prior to
loading the operand registers.
2
C-enabled peripherals. The I
The master drives this clock and the slaves receive
the clock. Note that SCLK can be gated and need not
be driven between SPI transactions.
driven by the master to all slaves on the SPI bus. Only
the selected slave clocks data from MOSI.
driven by the selected slave to the master. Only the
selected slave may drive this circuit. In fact, it is the
only circuit in the SPI bus arrangement that a slave is
ever permitted to drive.
active (generally low), the selected slave must drive
MISO.
2
C bus, drives the clock, and generates the START
Hardware Multiplier
2
C master device.
Hardware Multiplier
2
C bus is a 2-wire, bidirec-
MAXQ615
2
C bus master/
I
2
C Bus
12