MAXQ615-F00+ Maxim Integrated, MAXQ615-F00+ Datasheet - Page 15

• Manufacturer Part Number: MAXQ615-F00+
• Description: 16-bit Microcontrollers - MCU MICRO 16PIN
• Manufacturer: Maxim Integrated

Specifications of MAXQ615-F00+

• Rohs: yes
• Core: MAXQ20S
• Processor Series: MAXQ615
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 2 KB
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFN-16
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 12
• Number Of Timers: 3
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.4 V
• Part # Aliases: 90-M3900+F00

Table 2. Power-Fail Detection States During Normal Operation
If a reset is caused by a power-fail, the power-fail moni-
tor can be set to one of the following intervals:
• Always on—continuous monitoring
• 2
• 2
• 2
In the case where the power-fail circuitry is periodically
turned on, the power-fail detection is turned on for two
nanopower ring oscillator cycles. If V
Maxim Integrated
STATE
C
D
G
H
A
B
E
F
I
11
12
13
nanopower ring oscillator clocks (~256ms)
nanopower ring oscillator clocks (~512ms)
nanopower ring oscillator clocks (~1.024s)
POWER-FAIL
(Periodically)
(Periodically)
On
On
On
On
On
On
On
On
Off
REGULATOR
INTERNAL
Off
On
On
On
On
Off
On
Off
Off
DD
16-Bit MAXQ Microcontroller with
OSCILLATOR
> V
CRYSTAL
RST
Off
On
On
On
On
Off
On
Off
Off
during
RETENTION
SRAM
Yes
Yes
detection, V
er ring oscillator period. If V
the third nanopower ring period, the CPU exits the reset
state and resumes normal operation from utility ROM at
8000h after satisfying the crystal warmup period.
If a reset is generated by any other event, such as the
RESET pin being driven low externally or the watchdog
timer, the power-fail, internal regulator, and crystal
remain on during the CPU reset. In these cases, the
CPU exits the reset state in less than 20 crystal cycles
after the reset source is removed.
—
—
—
—
—
—
—
V
V
Crystal warmup time, t
CPU held in reset.
V
CPU normal operation.
Power drop too short.
Power-fail not detected.
V
PFI is set when V
this state for at least t
fail interrupt is generated (if enabled).
CPU continues normal operation.
V
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
V
Crystal warmup time, t
CPU resumes normal operation from 8000h.
V
Power-fail detected.
CPU goes into reset.
Power-fail monitor is turned on periodically.
V
Device held in reset.
No operation allowed.
Hardware Multiplier
DD
POR
DD
RST
POR
DD
POR
DD
DD
< V
> V
> V
< V
< V
< V
< V
< V
is monitored for an additional nanopow-
POR
RST
RST
POR
DD
DD
DD
DD
.
.
.
.
< V
< V
< V
< V
PFW
RST
RST
RST
RST
COMMENTS
.
.
.
.
DD
< V
PFW
XTAL_RDY
XTAL_RDY
DD
remains above V
, at which time a power-
MAXQ615
< V
PFW
.
.
and maintains
RST
for
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