MAXQ615-F00+ Maxim Integrated, MAXQ615-F00+ Datasheet - Page 14

• Manufacturer Part Number: MAXQ615-F00+
• Description: 16-bit Microcontrollers - MCU MICRO 16PIN
• Manufacturer: Maxim Integrated

Specifications of MAXQ615-F00+

• Rohs: yes
• Core: MAXQ20S
• Processor Series: MAXQ615
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 2 KB
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFN-16
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 12
• Number Of Timers: 3
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.4 V
• Part # Aliases: 90-M3900+F00

The lowest power mode of operation for the device is
stop mode. In this mode, CPU state and memories are
preserved, but the CPU is not actively running. Wake-up
sources include external I/O interrupts, the power-fail
warning interrupt, or a power-fail reset. Any time the
microcontroller is in a state where code does not need to
be executed, the user software can put the device into
stop mode. The nanopower ring oscillator is an internal
ultra-low-power (400nA), 8kHz ring oscillator that can be
used to drive a wake-up timer that exits stop mode. The
wake-up timer is programmable by software in steps of
125µs up to approximately 8s.
The power-fail monitor is always on during normal oper-
ation. However, it can be selectively disabled during stop
mode to minimize power consumption. This feature is
enabled using the power-fail monitor disable
Figure 5. Power-Fail Detection During Normal Operation
Maxim Integrated
INTERNAL RESET
(ACTIVE HIGH)
V
V
V
PFW
POR
RST
V
DD
A
B
C
t < t
D
PFW
16-Bit MAXQ Microcontroller with
Stop Mode
t R t
PFW
E
(PFD) bit in the PWCN register. The reset default state
for the PFD bit is 1, which disables the power-fail monitor
function during stop mode. If power-fail monitoring is dis-
abled (PFD = 1) during stop mode, the circuitry respon-
sible for generating a power-fail warning or reset is shut
down and neither condition is detected. Thus, the V
V
in the event that V
is generated. The power-fail monitor is enabled prior
to stop mode exit and before code execution begins.
If a power-fail warning condition (V
detected, the power-fail interrupt flag is set on stop mode
exit. If a power-fail condition is detected (V
the CPU goes into reset.
Figure
response during normal and stop mode operation.
RST
t R t
condition does not invoke a reset state. However,
5, 6, and
PFW
F
Hardware Multiplier
7
DD
show the power-fail detection and
falls below the POR level, a POR
G
Power-Fail Detection
t R t
PFW
MAXQ615
DD
H
< V
PFW
DD
I
< V
) is then
DD
RST
14
<
),