MAXQ615-F00+ Maxim Integrated, MAXQ615-F00+ Datasheet - Page 13

• Manufacturer Part Number: MAXQ615-F00+
• Description: 16-bit Microcontrollers - MCU MICRO 16PIN
• Manufacturer: Maxim Integrated

Specifications of MAXQ615-F00+

• Rohs: yes
• Core: MAXQ20S
• Processor Series: MAXQ615
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 2 KB
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFN-16
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 12
• Number Of Timers: 3
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.4 V
• Part # Aliases: 90-M3900+F00

Seven different multiply operations can be performed with-
out requiring direct intervention of the microcontroller core.
• Unsigned 16-bit multiplication
• Unsigned 16-bit multiplication and accumulation
• Unsigned 16-bit multiplication and subtraction
• Signed 16-bit multiplication
• Signed 16-bit multiplication and negate
• Signed 16-bit multiplication and accumulation
• Signed 16-bit multiplication and subtraction
Each of these operations is controlled and accessed
through six SFR registers. The 8-bit multiplier control reg-
ister (MCNT) selects the operation, data type, operand
count, optional hardware-based square function, write
option on the MC register, the overflow flag, and the clear
control for operand registers and accumulator. Loading
and unloading of the data is achieved through five 16-bit
SFR registers. Only one cycle is needed for computation.
This means that the result of an operation is ready in the
next cycle immediately following the loading of the last
operand. Back-to-back operations can be performed
without wait states between operations, independent of
data type and operand count.
All operations are synchronized to a single internal sys-
tem clock. The clock runs at approximately 20MHz. More
information on the clock timing is contained in the electri-
cal tables of this data sheet. Internal clock divisors are
available to reduce power consumption and or improve
compatibility with slower peripherals.
Approximately 25µs after V
reset), the internal oscillator stabilzes and code execu-
tion begins.
Embedded debug hardware and software are developed
and integrated to provide full in-circuit debugging capa-
bility in a user application environment. These hardware
and software features include:
• A debug engine
• A set of registers providing the ability to set break-
Maxim Integrated
points on register, code, or data using debug service
routines stored in ROM
DD
exceeds V
In-Circuit Debug
Clock Sources
16-Bit MAXQ Microcontroller with
RST
(a power-on
Collectively, these hardware and software features sup-
port two modes of in-circuit debug functionality:
• Background mode:
• Debug mode:
The interface to the debug engine is the JTAG interface.
To prevent unauthorized access, the debug engine pre-
vents access to system memory.
The idle mode suspends the processor so that no
instructions are fetched and no processing occurs.
Setting the IDLE bit in the CKCN register to 1 invokes
the idle mode. The instruction that executes this step is
the last instruction prior to halting the program counter.
Once in idle mode, all resources are preserved and all
clocks remain active with the enabled peripherals, and
power monitor continue to work, so the processor can
exit the idle state using any of the interrupt sources that
are enabled. The IDLE bit is cleared automatically once
the idle state is exited, allowing the processor to execute
the instruction that immediately follows the instruction
that set the IDLE bit.
To conserve power consumption, application can put
the processor into idle mode when code execution is not
required. One example of use is for SPI communication.
The application code can preload SPI FIFO with desired
number of bytes for transmission and then put the pro-
cessor into idle mode. The device continues with the SPI
transaction and only interrupts the processor when the
enabled SPI interrupts are generated. Another use is to
configure one of the timers to interrupt the device at a
predetermined interval. The application code can finish
its task and then put the processor into idle mode. The
timer then wakes up the processor when the specified
interval has elapsed.
CPU is executing the normal user program
Allows the host to configure and set up the in-circuit
debugger
The debugger takes over the control of the CPU
Read/write accesses to internal registers and mem-
ory
Single-step of the CPU for trace operation
Hardware Multiplier
Operating Modes
MAXQ615
Idle Mode
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