MAX195BEPE Maxim Integrated, MAX195BEPE Datasheet - Page 8

• Manufacturer Part Number: MAX195BEPE
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX195BEPE

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 85 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: Yes
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: PDIP N
• Maximum Power Dissipation: 842 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 5 V

after the end of the previous conversion and EOC will
go high on the following CLK falling edge (Figure 4).
The conversion clock (CLK) should have a duty cycle
between 25% and 75% at 1.7MHz (the maximum clock
frequency). For lower frequency clocks, ensure the min-
imum high and low times exceed 150ns. The minimum
clock rate for accurate conversion is 125Hz for temper-
atures up to +70°C or 1kHz at +125°C due to leakage
of the sampling capacitor array. In addition, CLK
should not remain high longer than 50ms at tempera-
tures up to +70°C or 500µs at +125°C. If CLK is held
high longer than this, RESET must be pulsed low to initi-
ate a recalibration because it is possible that state
information stored in internal dynamic memory may be
lost. The MAX195’s clock can be stopped indefinitely if
it is held low.
If the frequency, duty cycle, or other aspects of the
clock signal’s shape change, the offset created by cou-
pling between CLK and the analog inputs (AIN and
REF) changes. Recalibration corrects for this offset and
restores DC accuracy.
16-Bit, 85ksps ADC with 10µA Shutdown
Figure 4. Initiating Conversions—Less than 3 CLK cycles since end of previous conversion.
SPI/QSPI are trademarks of Motorola Corp.
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TRACK/HOLD
CONV
EOC
CLK
t
CC1
CONVERSION
ENDS
*
External Clock
t
CC2
t
CW
*
THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
t
CEL
t
AQ
The conversion result, clocked out MSB first, is avail-
able on DOUT only when CS is held low. Otherwise,
DOUT is in a high-impedance state. There are two ways
to read the data on DOUT. To read the data bits as they
are determined (at the CLK clock rate), hold CS low
during the conversion. To read results between conver-
sions, hold CS low and clock SCLK at up to 5MHz.
If you read the serial data bits as they are determined,
EOC frames the data bits (Figure 6). Conversion begins
with the first falling CLK edge, after CONV goes low
and the input signal has been acquired. Data bits are
shifted out of DOUT on subsequent falling CLK edges.
Clock data in on CLK’s rising edge or, if the clock
speed is greater than 1MHz, on the following falling
edge of CLK to meet the maximum CLK-to-DOUT tim-
ing specification. See the Operating Modes and
SPI™/QSPI™ Interfaces section for additional informa-
tion. Reading the serial data during the conversion
results in the maximum conversion throughput,
because a new conversion can begin immediately after
the input acquisition period following the previous con-
version.
CONVERSION
BEGINS
t
CEH
Output Data