ispLSI1048-50LQI Lattice, ispLSI1048-50LQI Datasheet
ispLSI1048-50LQI
Specifications of ispLSI1048-50LQI
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ispLSI1048-50LQI Summary of contents
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... Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number ispLSI 1048-50LQ ispLSI 1048-70LQ ispLSI 1048 ispLSI 1048-80LQ ispLSI 1048-50LQI 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Product Status Discontinued Phone (503) 268-8000 Internet: http://www.latticesemi.com Reference PCN PCN#13-10 FAX (503) 268-8347 ...
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... Optimized Global Routing Pool Provides Global Interconnectivity Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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Functional Block Diagram Figure 1. ispLSI 1048 Functional Block Diagram I/O I/O I/O I RESET Generic Output Routing Pool (ORP) Logic Blocks (GLBs I I I/O 3 I/O ...
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Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...
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... Typical values are and Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec- CC tion of this datasheet and Thermal Management section of this Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 1048 Figure 2. Test Load GND to 3.0V ≤ ...
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External Timing Parameters 5 2 TEST PARAMETER # DESCRIPTION COND. t pd1 A 1 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path pd2 Clock Frequency with Internal Feedback max ...
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Internal Timing Parameters 2 PARAMETER DESCRIPTION # Inputs t iobp I/O Register Bypass 20 t iolat I/O Latch Delay 21 t iosu I/O Register Setup Time before Clock 22 t ioh I/O Register Hold Time after Clock 23 t ...
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Internal Timing Parameters 2 PARAMETER DESCRIPTION # Outputs Output Buffer Delay t oen 48 I/O Cell OE to Output Enabled t odis I/O Cell OE to Output Disabled 49 Clocks t gy0 50 Clock Delay ...
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Timing Model I/O Cell Ded. In #26 I/O Reg Bypass I/O Pin #20 (Input) Input Register Q D RST #55 # 30, 31, 32 Reset Y1,2 Derivations of su, h and co ...
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Maximum GRP Delay vs GLB Loads Power Consumption Power consumption in the ispLSI 1048 device depends on two primary factors: the speed at which the device is operating, and the ...
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Pin Description NAME PQFP PIN NUMBERS I I/O 5 20, 21, 22, 23, 24, 25, I I/O 11 26, 27, 28, 29, 30, 31, I I/O 17 32, 33, 34, 35, 36, 37, I/O ...
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Pin Configuration ispLSI 1048 120-Pin PQFP Pinout Diagram I/O 94 ...
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Part Number Description ispLSI Device Family Device Number Speed MHz max MHz max MHz max ispLSI 1048 Ordering Information f Family max (MHz) 80 ispLSI ...