SiM3C157-B-GM Silicon Labs, SiM3C157-B-GM Datasheet - Page 42

• Manufacturer Part Number: SiM3C157-B-GM
• Description: ARM Microcontrollers - MCU 128KB LGA92
• Manufacturer: Silicon Labs

Specifications of SiM3C157-B-GM

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SIM3C1xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 80 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 42 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LGA-92
• Mounting Style: SMD/SMT
• Interface Type: 2 x I2C, I2S, 3 x SPI, 2 x USART, 2 x UART
• Number Of Programmable I/os: 75
• Number Of Timers: 12 x 32 bit
• Supply Voltage - Max: 3.6 V

SiM3C1xx
4.6. Communications Peripherals
4.6.1. External Memory Interface (EMIF0)
The External Memory Interface (EMIF0) allows external parallel asynchronous devices, like SRAMs and LCD
controllers, to appear as part of the system memory map. The EMIF0 module includes the following features:
4.6.2. USART (USART0, USART1)
The USART uses two signals (TX and RX) and a predetermined fixed baud rate to communicate with a single
device. In addition to these signals, the USART0 module can optionally use a clock (UCLK) or hardware
handshaking (RTS and CTS).
The USART module provides the following features:
4.6.3. UART (UART0, UART1)
The USART uses two signals (TX and RX) and a predetermined fixed baud rate to communicate with a single
device.
The UART module provides the following features:
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Provides a memory mapped view of multiple external devices.
Support for byte, half-word and word accesses regardless of external device data-width.
Error indicator for certain invalid transfers.
Minimum external timing allows for 3 clocks per write or 4 clocks per read.
Output bus can be shared between non-muxed and muxed devices.
Available extended address output allows for up to 24-bit address with 8-bit parallel devices.
Support for 8-bit and 16-bit (muxed-mode only) devices with up to two chip-select signals.
Support for internally muxed devices with dynamic address shifting.
Fully programmable control signal waveforms.
Independent transmitter and receiver configurations with separate 16-bit baud rate generators.
Synchronous or asynchronous transmissions and receptions.
Clock master or slave operation with programmable polarity and edge controls.
Up to 5 Mbaud (synchronous or asynchronous, TX or RX, and master or slave) or 1 Mbaud Smartcard (TX
or RX).
Individual enables for generated clocks during start, stop, and idle states.
Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads
and writes.
Data bit lengths from 5 to 9 bits.
Programmable inter-packet transmit delays.
Auto-baud detection with support for the LIN SYNC byte.
Automatic parity generation (with enable).
Automatic start and stop generation (with separate enables).
Transmit and receive hardware flow-control.
Independent inversion correction for TX, RX, RTS, and CTS signals.
IrDA modulation and demodulation with programmable pulse widths.
Smartcard ACK/NACK support.
Parity error, frame error, overrun, and underrun detection.
Multi-master and half-duplex support.
Multiple loop-back modes supported.
Multi-processor communications support.
Independent transmitter and receiver configurations with separate 16-bit baud-rate generators.
Asynchronous transmissions and receptions.
Up to 5 Mbaud (TX or RX) or 1 Mbaud Smartcard (TX or RX).
Rev.1.0