MPC8308VMAFDA Freescale Semiconductor, MPC8308VMAFDA Datasheet - Page 32

• Manufacturer Part Number: MPC8308VMAFDA
• Description: Microprocessors - MPU E300 MP PbFr 333
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAFDA

• Rohs: yes
• Processor Series: MPC8308
• Core: e300
• Maximum Clock Frequency: 333 MHz
• Interface Type: I2C, JTAG, UART
• Operating Supply Voltage: 0.95 V to 1.05 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-473

High-Speed Serial Interfaces (HSSI)
This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with the device’s SerDes reference clock
input’s DC requirement.
10.2.4
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50  to match the
transmission line and reduce reflections which are a source of noise to the system.
This table describes some AC parameters for PCI Express protocol.
32
At recommended operating conditions with XCOREVDD= 1.0V ± 5%
Rising Edge Rate
Falling Edge Rate
Differential Input High Voltage
Differential Input Low Voltage
Single-Ended
CLK Driver Chip
Clock Driver
AC Requirements for SerDes Reference Clocks
CLK_Out
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Parameter
Figure 23. Single-Ended Connection (Reference Only)
33 
Table 32. SerDes Reference Clock AC Parameters
Total 50 Assume clock driver’s
output impedance is about 16 
50 
100 differential PWB trace
Rise Edge Rate
Fall Edge Rate
Symbol
V
V
SD_REF_CLK
SD_REF_CLK
IH
IL
+200
Min
1.0
1.0
—
50 
50 
–200
Max
MPC8308
4.0
4.0
—
Freescale Semiconductor
SerDes Refer.
CLK Receiver
Unit
V/ns
V/ns
mV
mV
Notes
2, 3
2, 3
2
2