MPC8308VMAFDA Freescale Semiconductor, MPC8308VMAFDA Datasheet - Page 37

• Manufacturer Part Number: MPC8308VMAFDA
• Description: Microprocessors - MPU E300 MP PbFr 333
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAFDA

• Rohs: yes
• Processor Series: MPC8308
• Core: e300
• Maximum Clock Frequency: 333 MHz
• Interface Type: I2C, JTAG, UART
• Operating Supply Voltage: 0.95 V to 1.05 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-473

AC coupling capacitor
Crosslink random timeout
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in
3. A T
4. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode return
5. Measured between 20%–80% at transmitter package pins into a test load as shown in
6. See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a.
7. See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a.
11.4.2
The TX eye diagram in
(Figure
that must be met for the transmitter. Both diagrams must be aligned in time using the jitter median to locate
the center of the eye diagram. The different eye diagrams differ in voltage depending on whether it is a
transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit is always
relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
UI.
Freescale Semiconductor
250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in
transmitter collected over any 250 consecutive TX UIs. The T
jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The
jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to
the averaged time value.
loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to
all valid input levels. The reference impedance for return loss measurements is 50  to ground for both the D+ and D– line (that
is, as measured by a vector network analyzer with 50- probes, see
for the return loss measurement.
TX-EYE
Parameter
29) in place of any real PCI Express interconnect + RX component. There are two eye diagrams
= 0.70 UI provides for a total sum of deterministic and random jitter budget of T
Transmitter Compliance Eye Diagrams
It is recommended that the recovered TX UI be calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (that is, least squares and median deviation fits).
Table 34. Differential Transmitter (TX) Output Specifications (continued)
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Figure 27
T
Symbol
crosslink
C
TX
is specified using the passive compliance/test measurement load
All Transmitters shall be AC coupled.
The AC coupling is required either within
the media or within the transmitting
component itself. An external capacitor
of 100nF is recommended.
This random timeout helps resolve
conflicts in crosslink configuration by
eventually resulting in only one
Downstream and one Upstream Port.
NOTE
Comments
TX-EYE-MEDIAN-to-MAX-JITTER
Figure
29). Note that the series capacitors, C
Figure 29
Figure
median is less than half of the total TX
Min
TX-JITTER-MAX
75
0
Figure 29
27.)
Typical
for both V
—
—
and measured over any
= 0.30 UI for the
TX-D+
Max
200
1
and V
TX
PCI Express
Units Note
, is optional
ms
nF
TX-D-
—
.
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