STM32F051C8T7TR STMicroelectronics, STM32F051C8T7TR Datasheet - Page 75

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STM32F051C8T7TR

Manufacturer Part Number
STM32F051C8T7TR
Description
ARM Microcontrollers - MCU Entry-level ARM Cortex-M0 MCU 64Kb
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F051C8T7TR

Rohs
yes

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Electrical characteristics
6.3.14
76/105
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in
performed under ambient temperature and VDD supply voltage conditions summarized in
Table
Table 53.
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
Figure 21. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
V
V
V
V
V
NF(NRST)
IH(NRST)
IL(NRST)
Symbol
F(NRST)
hys(NRST)
to the series resistance must be minimum
Table
R
20.
PU
53. Otherwise the reset will not be taken into account by the device.
(1)
(1)
(1)
(1)
PU
NRST pin characteristics
(see
NRST Input low level voltage
NRST Input high level voltage
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse
Table
50).
Parameter
Doc ID 022265 Rev 3
(~10% order)
(2)
.
Conditions
V
IN
Table 53
=
V
SS
are derived from tests
IL(NRST)
–0.3
Min
300
30
2
-
-
max level specified in
Typ
200
40
-
-
-
-
V
STM32F051x
DD
Max
100
0.8
50
-
-
+0.3
Unit
mV
ns
ns
V

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