MK30DN512ZVLQ10R Freescale Semiconductor, MK30DN512ZVLQ10R Datasheet - Page 44

• Manufacturer Part Number: MK30DN512ZVLQ10R
• Description: ARM Microcontrollers - MCU KINETIS 512K LCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLQ10R

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Peripheral operating requirements and behaviors
1. Typical values assume V
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
4. For single ended configurations the input impedance of the driven input is R
5. The analog source resistance (R
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
6.6.1.4 16-bit ADC with PGA characteristics
44
I
Symbol
Symbol
I
DDA_PGA
DC_PGA
reference only and are not tested in production.
than the output of the VREF module, the VREF module must be disabled.
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
time should be allowed for F
8 MHz ADC clock.
C
rate
ADC conversion
rate
Description
Supply current
Input DC current
Description
Table 29. 16-bit ADC with PGA operating conditions (continued)
DDA
Table 30. 16-bit ADC with PGA characteristics
K30 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
in
≤ 13 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
16 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
Conditions
= 3.0 V, Temp = 25°C, f
=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
Low power
(ADC_PGA[PGALPb]=0)
Gain =1, V
V
Gain =64, V
V
Conditions
CM
CM
AS
=0.5V
=0.1V
), external to MCU, should be kept as minimum as possible. Increased R
REFPGA
Table continues on the next page...
REFPGA
=1.2V,
=1.2V,
ADCK
18.484
37.037
Min.
= 6 MHz unless otherwise stated. Typical values are for
Min.
—
—
—
Typ.
—
—
1
PGAD
Typ.
1.54
0.57
420
/2
1
Max.
450
250
Max.
644
—
—
Freescale Semiconductor, Inc.
Ksps
Ksps
Unit
Unit
μA
μA
μA
A
AS
causes drop
Notes
Notes
7
8
2
3