MK30DN512ZVLQ10R Freescale Semiconductor, MK30DN512ZVLQ10R Datasheet - Page 56

• Manufacturer Part Number: MK30DN512ZVLQ10R
• Description: ARM Microcontrollers - MCU KINETIS 512K LCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLQ10R

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Peripheral operating requirements and behaviors
6.8.4 Inter-Integrated Circuit Interface (I
1. The master mode I
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10ns and Output Load = 50pf
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I
56
Hold time (repeated) START condition.
After this period, the first clock pulse is
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t
= 1000 + 250 = 1250 ns (according to the Standard mode I
Set-up time for a repeated START
Data hold time for I
Rise time of SDA and SCL signals
Pulse width of spikes that must be
Bus free time between STOP and
Fall time of SDA and SCL signals
Set-up time for STOP condition
HIGH period of the SCL clock
LOW period of the SCL clock
suppressed by the input filter
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
SCL Clock Frequency
START condition
Data set-up time
Characteristic
generated.
condition
2
C bus device can be used in a Standard mode I2C bus system, but the requirement t
2
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
C bus devices
Figure 22. DSPI classic SPI timing — slave mode
K30 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
DS13
DS15
t
t
t
t
t
Symbol
HD
SU
HD
SU
SU
t
t
f
t
First data
First data
HIGH
LOW
Table 42. I
; STO
t
SCL
; STA
; STA
; DAT
; DAT
BUF
SP
t
t
r
f
DS14
Minimum
DS10
250
DS12
N/A
4.7
4.7
4.7
0
—
—
Standard Mode
2
0
4
4
4
1
C bus specification) before the SCL line is released.
2
4
C timing
Data
Data
Maximum
2
C) timing
3.45
1000
100
300
N/A
—
—
—
—
—
—
—
2
DS11
DS9
20 +0.1C
20 +0.1C
Minimum
Last data
Last data
100
0.6
1.3
0.6
0.6
0.6
1.3
0
0
0
3
2,
Fast Mode
5
b
b
6
5
Freescale Semiconductor, Inc.
DS16
Maximum
0.9
SU; DAT
400
300
300
50
—
—
—
—
—
—
—
1
≥ 250 ns must
rmax
+ t
Unit
kHz
SU; DAT
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns