MPC8536EAVTATLA Freescale Semiconductor, MPC8536EAVTATLA Datasheet - Page 91

• Manufacturer Part Number: MPC8536EAVTATLA
• Description: Microprocessors - MPU 8536 ENCRYPTED
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536EAVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common
mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values,
the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each
signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential
swing (V
mV and –500 mV, in other words, V
(V
2.20.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clocks for PCI Express are SD1_REF_CLK and, SD1_REF_CLK. The SerDes reference
clocks for the SATA and SGMII interfaces are SD2_REF_CLK and, SD2_REF_CLK.
The following sections describe the SerDes reference clock requirements and some application information.
2.20.2.1
Figure 58
Freescale Semiconductor
DIFFp
6.
•
•
) is 500 mV. The peak-to-peak differential voltage (V
Common Mode Voltage, V
The supply voltage requirements for X2V
SerDes Reference Clock Receiver Reference Circuit Structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in
A Volts
OD
B Volts
shows a receiver reference diagram of the SerDes reference clocks.
) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500
Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-Ω termination to SGND (xcorevss)
followed by on-chip AC-coupling.
SerDes Reference Clocks
SerDes Reference Clock Receiver Characteristics
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Figure 57. Differential Voltage Definitions for Transmitter or Receiver
SD n _TX or
SD n _RX
SD n _TX or
SD n _RX
peak. For example, the output differential peak-peak voltage can also be calculated as V
= 2*|V
circuit and ground. In this example, for SerDes output, V
/ 2, which is the arithmetic mean of the two complimentary output voltages within a differential
pair. In a system, the common mode voltage may often differ from one component’s output to the
other’s input. Sometimes, it may be even different between the receiver input and driver output
circuits within the same component. It is also referred as the DC offset in some occasion.
OD
OD
cm
|.
is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage
Differential Peak-Peak Voltage, V
DD
Differential Swing, V
Differential Peak Voltage, V
are specified in
DIFFp-p
) is 1000 mV p-p.
Table 2
ID
or V
DIFFpp
and
OD
DIFFp
= 2*V
= A – B
Table
= |A – B|
cm_out
DIFFp
3.
= V
(not shown)
SDn_TX
Electrical Characteristics
V
+ V
cm
= (A + B) / 2
SDn_TX
Figure
TX-DIFFp-p
= (A + B)
58.
91