MAX5805AAUB+ Maxim Integrated, MAX5805AAUB+ Datasheet - Page 16

• Manufacturer Part Number: MAX5805AAUB+
• Description: Digital to Analog Converters - DAC 12Bit 1Ch V Buffered Precision DAC
• Manufacturer: Maxim Integrated

Specifications of MAX5805AAUB+

• Rohs: yes
• Number Of Converters: 1
• Number Of Dac Outputs: 1
• Resolution: 12 bit
• Interface Type: Serial (I2C)
• Settling Time: 6 us
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX-10
• Maximum Power Dissipation: 707.3 mW
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage Buffered
• Supply Current: 190 uA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

data registers are cleared to their default/return values
as defined by the configuration settings. Other user-
configuration settings are not affected.
Some I
during the transfer sequence. If CLR is issued during a
command write sequence, any gated commands within
the sequence are ignored. If CLR is issued during an
I
as normal, however the data read back may be stale.
The user may determine the state of the CLR input by
issuing a status read. In all cases, the I
continues to function according to protocol, however
slave ACK pulses beyond the command acknowledge
are not sent for gated write commands (notifying the
FP that these instructions are being ignored). Any non-
gated commands appearing in the transfer sequence
are fully acknowledged and executed. In order for the
gating condition to be removed, remove CLR prior
to a recognized START condition, meeting t
requirements.
Use of the GATE mode provides a means of momentarily
holding the DAC in a user-selectable default/return state,
returning the DAC to the last programmed state upon
removal. The MAX5803/MAX5804/MAX5805 also feature
a software-accessible GATE command. While asserted
in GATE mode, the AUX pin does not interfere with
RETURN, CODE, or DAC register updates and related
load activity. The user may determine the gate status of
the device by issuing a status read. I
CODE and DAC register content while gated continue to
return the current register values, which may differ from
the actual DAC output level.
The MAX5803/MAX5804/MAX5805 provide a dedicated
asynchronous LDAC (active-low) input. The LDAC input
performs an asynchronous level sensitive LOAD operation
when pulled low. Use of the LDAC input mode provides
a means of updating multiple devices together as a
group. Users wishing to control the DAC update instance
independently of the I/O instruction should hold LDAC
high during programming cycles. Once programming
is complete, LDAC may be strobed and the new CODE
register content is loaded into the DAC latch output.
Users wishing to load new DAC data in direct response
to I/O CODE register activity should connect LDAC
permanently low; in this configuration, the MAX5803/
Maxim Integrated
2
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I
C command read sequence, the exchange continues
2
C interface commands are gated by CLR activity
2
C readbacks of
LDAC Input
2
GATE Mode
C interface
CLRSTA
MAX5803/MAX5804/MAX5805
MAX5804/MAX5805 DAC output updates in response to
each completed I/O CODE instruction update edge. A
software LOAD command is also provided.
The LDAC operation does not interact with the user
interface directly. However, in order to achieve the best
possible glitch performance, timing with respect to the
interface update edge should follow t
when issuing CODE commands. Using the software
LOAD command with the Broadcast ID provides a
software-based means of synchronously updating several
MAX5803/MAX5804/MAX5805 devices on a shared bus.
The MAX5803/MAX5804/MAX5805 feature a separate
supply pin (V
If present, connect V
processor.
The MAX5803/MAX5804/MAX5805 feature an I
SMBusK-compatible, 2-wire serial interface consisting of
a serial data line (SDA) and a serial clock line (SCL). SDA
and SCL enable communication between the MAX5803/
MAX5804/MAX5805 and the master at clock rates up
to 400kHz.
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
MAX5803/MAX5804/MAX5805 by transmitting the proper
slave address followed by the command byte and then
the data word. Each transmit sequence is framed by a
START (S) or Repeated START (Sr) condition and a STOP
(P) condition. Each word transmitted to the MAX5803/
MAX5804/MAX5805 is 8 bits long and is followed by an
acknowledge clock pulse.
A master reading data from the MAX5803/MAX5804/
MAX5805 must transmit the proper slave address
followed by a series of nine SCL pulses for each byte
of data requested. The MAX5803/MAX5804/MAX5805
transmit data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a START
or Repeated START condition, a not acknowledge, and
a STOP condition. SDA operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kI is
required on SDA. SCL operates only as an input. A pullup
resistor, typically 4.7kI, is required on SCL if there are
multiple masters on the bus, or if the single master has
an open-drain SCL output.
Figure 1
DDIO
) for the digital interface (1.8V to 5.5V).
DDIO
shows the 2-wire interface timing
to the I/O supply of the host
2
I
2
C Interface
C Serial Interface
LDH
V
specifications
DDIO
Input
2
C-/
16