MAX5805AAUB+ Maxim Integrated, MAX5805AAUB+ Datasheet - Page 20

• Manufacturer Part Number: MAX5805AAUB+
• Description: Digital to Analog Converters - DAC 12Bit 1Ch V Buffered Precision DAC
• Manufacturer: Maxim Integrated

Specifications of MAX5805AAUB+

• Rohs: yes
• Number Of Converters: 1
• Number Of Dac Outputs: 1
• Resolution: 12 bit
• Interface Type: Serial (I2C)
• Settling Time: 6 us
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX-10
• Maximum Power Dissipation: 707.3 mW
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage Buffered
• Supply Current: 190 uA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

Figure 6. Standard I
Sample command sequences are shown in
first command transfer is given in write mode with R/W =
0 and must be run to completion to qualify for interface
verification readback. There is now a STOP/START pair
or Repeated START condition required, followed by the
readback transfer with R/W = 1 to indicate a read and
an acknowledge clock from the MAX5803/MAX5804/
MAX5805. The master still has control of the SCL line but
the MAX5803/MAX5804/MAX5805 take over the SDA line.
The final three bytes in the frame contain the command
and register data written in the first transfer presented
for readback, followed by a STOP condition. If additional
bytes beyond those required to read back the requested
Table 2. Standard I
Table 3. DAC Data Bit Positions
Maxim Integrated
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
SDA
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
SCL
Voltage DACs with Internal Reference and I
0
0
1
1
1
1
MAX5803
MAX5804
MAX5805
PART
START
COMMAND BYTE (REQUEST)
0
1
0
0
0
0
Any other command
0 0 1 1 0 A1 A0 W A
0
1
0
0
1
1
BYTE #1: I
WRITE ADDRESS
B15
D11
D7
D9
ADDRESS
0
1
0
1
0
1
2
2
C Register Read Sequence
C SLAVE
B14
D10
X
X
X
X
X
X
D6
D8
A
2
X
X
X
X
X
X
ACK. GENERATED BY MAX5803/MAX5804/MAX5805
C User Readback Data
B13
D5
D7
D9
N N N
X
X
X
X
X
X
BYTE #2: COMMAND1
WRITE COMMAND1
B12
D4
D6
D8
X
X
X
X
X
X
N N N N N
BYTE
CLR
B11
0
D3
D5
D7
Figure
READBACk DATA HIGH BYTE
1
A
B10
D2
D4
D6
REPEATED
START
MAX5803/MAX5804/MAX5805
7. The
0
RETURN[11:4]
CODE[11:4]
DAC[11:4]
DAC[11:4]
DAC[11:4]
0 0 1 1 0 A1 A0 R A D D D D D D D D
B9
D1
D3
D5
BYTE #3: I
1
1
READ ADDRESS
ADDRESS
0
B8
D0
D2
D4
data are provided, the MAX5803/MAX5804/MAX5805 will
continue to read back ones.
It is not necessary for the write and read mode transfers
to occur immediately in sequence. I
other devices do not impact the MAX5803/MAX5804/
MAX5805 readback mode. Toggling between readback
modes is based on the length of the preceding write
mode transfer. Combined format I
is resumed if a write command greater than two bytes
but less than four bytes is supplied. For commands writ-
ten using multiple register write sequences, only the last
command executed is read back. For each command
written, the readback sequence can only be completed
2
C SLAVE
RF[3:0]
REV_ID[2:0]
B7
D1
D3
X
(000)
A
ACK. GENERATED BY I
BYTE #4: DATA1 HIGH
B6
D0
D2
X
B8
BYTE (B[15:8])
READ DATA
B7
PD[1:0]
B5
D1
X
X
RETURN[3:0]
CODE[3:0]
READBACk DATA LOW BYTE
DAC[3:0]
DAC[3:0]
DAC[3:0]
B6
2
C MASTER
B4
D0
X
X
A
B5
MAX5803 = 0x8A
MAX5804 = 0x92
MAX5805 = 0x82
D D D D D D D D ~A
PART_ID[7:0]
2
AB[2:0]
LOWBYTE (B[7:0])
BYTE #5: DATA1
B3
X
X
X
B4
C Interface
2
READ DATA
C readback operation
2
C transfers involving
B3
0
0
0
0
0
B2
X
X
X
B2
0
0
0
0
0
B1
DF[2:0]
X
X
X
B1
0
0
0
0
0
STOP
B0
X
X
B0
X
0
0
0
0
0
20