MAX5805AAUB+ Maxim Integrated, MAX5805AAUB+ Datasheet - Page 17

• Manufacturer Part Number: MAX5805AAUB+
• Description: Digital to Analog Converters - DAC 12Bit 1Ch V Buffered Precision DAC
• Manufacturer: Maxim Integrated

Specifications of MAX5805AAUB+

• Rohs: yes
• Number Of Converters: 1
• Number Of Dac Outputs: 1
• Resolution: 12 bit
• Interface Type: Serial (I2C)
• Settling Time: 6 us
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX-10
• Maximum Power Dissipation: 707.3 mW
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage Buffered
• Supply Current: 190 uA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5803/
MAX5804/MAX5805 from high voltage spikes on the
bus lines and minimize crosstalk and undershoot of
the bus signals. The MAX5803/MAX5804/MAX5805 can
accommodate bus voltages higher than V
a limit of 5.5V; bus voltages lower than V
recommended and may result in significantly increased
interface currents. The MAX5803/MAX5804/MAX5805
digital inputs are double buffered. Depending on the
command issued through the serial interface, the CODE
register(s) can be loaded without affecting the DAC
register(s) using the write command. To update the DAC
registers, either drive the AUX input low while in LDAC
mode to asynchronously update the DAC output, or use
the software LOAD command.
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high
START condition from the master signals the beginning
of a transmission to the MAX5803/MAX5804/MAX5805.
The master terminates transmission and frees the bus
by issuing a STOP condition. The bus remains active if
a Repeated START condition is generated instead of a
STOP condition.
The MAX5803/MAX5804/MAX5805 recognize a STOP
condition at any point during data transmission except
if the STOP condition occurs in the same high pulse
as a START condition. Transmissions ending in an
early STOP condition do not impact the internal device
settings. If STOP occurs during a readback byte, the
transmission is terminated and a later read mode request
begins transfer of the requested register data from the
beginning (this applies to combined format I
Table 1. I
Maxim Integrated
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I
ADDR
GND
N.C.
V
DD
I
2
C Early STOP and Repeated START
2
C Slave Address LSBs
I
2
C START and STOP Conditions
A[6:2] = 00110
A1
1
1
0
Conditions
(Figure
DD
A0
DD
1
0
0
2
are not
C read
MAX5803/MAX5804/MAX5805
up to
2). A
mode transfers only, interface verification mode transfers
will be corrupted, see
The slave address is defined as the seven most significant
bits (MSBs) followed by the R/W bit. See
five most significant bits are 00110 with the 2 LSBs
determined by ADDR as shown in
R/W bit to 1 configures the MAX5803/MAX5804/MAX5805
for read mode. Setting the R/W bit to 0 configures
the MAX5803/MAX5804/MAX5805 for write mode. The
slave address is the first byte of information sent to the
MAX5803/MAX5804/MAX5805 after the START condition.
The MAX5803/MAX5804/MAX5805 have the ability to
detect an unconnected state on the ADDR input for
additional address flexibility; if leaving the ADDR input
unconnected, be certain to minimize all loading on the
pin (i.e. provide a landing for the pin, but do not allow any
board traces). Using the ADDR input, up to three devices
can be run on a single I
Figure 2. I
SDA
SCL
INVALID START/STOP PULSE PAIRINGS - ALL WILL BE RECOGNIZED AS STARTS
2
P
C START, Repeated START, and STOP Conditions
S
S
VALID START, REPEATED START, AND STOP PULSES
S
Figure
2
C bus
P
Sr
2.)
2
C Interface
I
P
2
C Slave Address
Table
S
P
1. Setting the
Figure
P
4. The
17