M24LR04E-RMC6T/2 STMicroelectronics, M24LR04E-RMC6T/2 Datasheet - Page 36
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M24LR04E-RMC6T/2
Manufacturer Part Number
M24LR04E-RMC6T/2
Description
EEPROM 4-Kbit EEProm 400kHz 13.56Mhz 1.8 to 5.5V
Manufacturer
STMicroelectronics
Datasheet
1.M24LR04E-RDW6T2.pdf
(142 pages)
Specifications of M24LR04E-RMC6T/2
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C device operation
Minimizing system delays by polling on ACK
During the internal write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum I²C write time (t
shown in
can be used by the bus master.
The sequence, as shown in
1.
2.
3.
Initial condition: a write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus
master goes back to Step 1. If the device has terminated the internal write cycle, it
responds with an Ack, indicating that the device is ready to receive the second part of
the instruction (the first byte of this instruction having been sent during Step 1).
Table 122
, but the typical time is shorter. To make use of this, a polling sequence
Figure
Doc ID 022208 Rev 5
10, is:
M24LR04E-R
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