LFE2-6E-7F256C Lattice, LFE2-6E-7F256C Datasheet - Page 25
LFE2-6E-7F256C
Manufacturer Part Number
LFE2-6E-7F256C
Description
FPGA - Field Programmable Gate Array 6K LUTs 190 I/O DSP 1.2V -7
Manufacturer
Lattice
Datasheet
1.LFE2-70E-7F900C.pdf
(104 pages)
Specifications of LFE2-6E-7F256C
Number Of I/os
190
Maximum Operating Frequency
420 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-256
Minimum Operating Temperature
0 C
Factory Pack Quantity
450
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-6E-7F256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
MAC sysDSP Element
In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. The Accumulators in the
DSP blocks in LatticeECP2 family can be initialized dynamically. A registered overflow signal is also available. The
overflow conditions are provided later in this document. Figure 2-21 shows the MAC sysDSP element.
Figure 2-21. MAC sysDSP
Multiplicand
Multiplier
SignedAB
Addn
Accumsload
Serial Register B in
n
Input Data
Register B
n
n
SROB
n
Register
Register
Register
Input
Input
Input
m
Input Data
Register A
m
n
SROA
Serial Register A in
m
Register
Register
Register
Pipeline
Pipeline
Pipeline
m
n
2-22
To Accumulator
To Accumulator
To Accumulator
Multiplier
Register
Pipeline
x
(default)
m+n
Accumulator
LatticeECP2 Family Data Sheet
CLK (CLK0,CLK1,CLK2,CLK3)
RST(RST0,RST1,RST2,RST3)
CE (CE0,CE1,CE2,CE3)
m+n+16
(default)
Preload
(default)
m+n+16
Architecture
Output
Overflow
signal
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