LFE2-6E-7F256C Lattice, LFE2-6E-7F256C Datasheet - Page 41
LFE2-6E-7F256C
Manufacturer Part Number
LFE2-6E-7F256C
Description
FPGA - Field Programmable Gate Array 6K LUTs 190 I/O DSP 1.2V -7
Manufacturer
Lattice
Datasheet
1.LFE2-70E-7F900C.pdf
(104 pages)
Specifications of LFE2-6E-7F256C
Number Of I/os
190
Maximum Operating Frequency
420 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-256
Minimum Operating Temperature
0 C
Factory Pack Quantity
450
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-6E-7F256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 2-34. LatticeECP2 Banks
LatticeECP2 devices contain two types of sysIO buffer pairs.
1. Top (Bank 0 and Bank 1) sysIO Buffer Pairs (Single-Ended Outputs Only)
2. Bottom (Bank 4 and Bank 5) sysIO Buffer Pairs (Single-Ended Outputs Only)
The sysIO buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of
single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con-
figured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
The sysIO buffer pairs in the bottom banks of the device consist of two single-ended output drivers and two
sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also
be configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on bottom banks have programmable PCI clamps.
V
V REF1(7)
V REF2(7)
V CCIO6
V REF1(6)
V REF2(6)
CCIO7
GND
GND
Bank 0
Bank 5
BOTTOM
TOP
2-38
Bank 1
Bank 4
LatticeECP2 Family Data Sheet
V CCIO2
V REF1(2)
V REF2(2)
V CCIO3
V REF1(3)
V REF2(3)
V CCIO8
GND
GND
GND
Architecture
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