iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 105

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

Lattice Semiconductor Corporation
www.latticesemi.com
Internal Configuration Oscillator Frequency
Configuration Timing
Table 57
Table 58
slowest frequency for a given oscillator mode from
Table 1
mode based on the performance of the configuration data source.
Table 59
f
f
f
t
t
t
Symbol
Symbol
OSCD
OSCL
OSCH
Symbol
CONFIGL
CRESET_B
DONE_IO
which includes full RAM4K block initialization. The configuration bitstream selects the desired oscillator
shows the operating frequency for the iCE65’s internal configuration oscillator.
Table 58:
provides timing for the CRESET_B and CDONE pins.
shows the maximum time to configure an iCE65 device, by oscillator mode. The calculations use the
Time from when
minimum Power-on
Reset (POR) threshold is
reached until user
application starts.
Default
Low
Frequency
High
Frequency
Off
CREST_B
CDONE
From
Oscillator
High
Mode
Description
Maximum SPI Master or NVCM Configuration Timing by Oscillator Mode
PIO pins
CREST_B
active
To
Frequency (MHz)
Min.
Table 59: General Configuration Timing
Table 57: Internal Oscillator Frequency
4.0
14
21
0
Minimum CRESET_B Low pulse width required to restart
configuration, from falling edge to rising edge
Number of configuration clock cycles after CDONE goes
High before the PIO pins are activated.
SPI Peripheral Mode (Clock = SPI_SCK, cycles measured
rising-edge to rising-edge)
NVCM or SPI Master Mode by internal
oscillator frequency setting (Clock =
internal oscillator)
iCE65L01
iCE65L04
iCE65L08
Device
Max.
6.8
21
31
0
Default oscillator frequency. Slow enough to safely operate
with any SPI serial PROM.
Supported by most SPI serial Flash PROMs
Supported by some high-speed SPI serial Flash PROMs
Oscillator turned off by default after configuration to save
power.
Table 57
Description
Default
115
230
53
and the maximum configuration bitstream size from
Low Freq.
110
25
55
Default
Low
High
Description
High Freq.
11
25
50
SPI_SCK frequency
Min.
7.20
2.34
1.59
200
—
All Grades
Depends on
(2.42, 30-MAR-2011)
Units
ms
ms
ms
12.25
Max.
3.50
2.33
49
—
cycles
Units
Clock
ns
µs
µs
µs
105