iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 11

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

Lattice Semiconductor Corporation
www.latticesemi.com
I/O Banks 0, 1, 2, SPI and Bank 3 of iCE65L01
I/O Bank 3 of iCE65L04 and iCE65L08
If not connected to an external SPI PROM, the four pins associated with the
be used as PIO pins, supplied by the SPI_VCC input, essentially forming a fifth “mini” I/O bank. If using an SPI
Flash PROM, then connect SPI_VCC to 3.3V.
Table 6
in which bank(s) the standard is supported. I/O Banks 0, 1, 2 and SPI interface support the same standards. I/O
Bank 3 has additional capabilities in iCE65L04 and iCE65L08, including support for MDDR memory standards and
LVDS differential I/O.
IBIS Models for I/O Banks 0, 1, 2 and the SPI Bank
The IBIS (I/O Buffer Information Specification) file that describes the output buffers used in I/O Banks 0, 1, 2, SPI
Bank and Bank 3 of iCE65L01 is available from the following link.
I/O Bank 3, located along the left edge of the die, has additional special I/O capabilities to support memory
components and differential I/O signaling (LVDS).
The SSTL2 and SSTL18 I/O standards require the VREF voltage reference input pin which is only available on the
CB284 package. Also see
I/O Standard

Table 6:
5V Input Tolerance
LVCMOS15 outputs
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
SSTL18_II
SSTL18_I
SSTL2_II
SSTL2_I
MDDR
highlights the available I/O standards when using an iCE65 device, indicating the drive current options, and
I/O Standard
IBIS Models for I/O Banks 0, 1, 2, SPI Bank and Bank 3 of iCE65L01
LVDS
LVCMOS33
LVCMOS25
LVCMOS18
I/O Standards for I/O Banks 0, 1, 2, SPI Interface Bank, and Bank 3 of iCE65L01
Table 7:
Table 51
Voltage
I/O Standards for I/O Bank 3 Only of iCE65L04 and iCE65L08
Supply
3.3V
2.5V
1.8V
1.5V
2.5V
1.8V
1.8V
2.5V
for electrical characteristics.
Supply Voltage
3.3V
3.3V
2.5V
1.8V
1.5V
VREF Pin (CB284 or
DiePlus) Required?
Yes
Yes
No
No
No
No
No
No
Table 7
lists the various I/O standards supported by I/O Bank 3.
Drive Current (mA)
Drive Current (mA)
±11
N/A
±8
±5
±4
Target
SPI Master Configuration Interface
±16.2
±13.4
±8.1
±6.7
±16
±12
±10
±10
N/A
±8
±8
±4
±8
±4
±2
±4
±2
±8
±4
±2
(2.42, 30-MAR-2011)
Attribute Name
SB_SSTL2_CLASS_2
SB_SSTL2_CLASS_1
SB_LVCMOS
SB_LVCMOS25_16
SB_LVCMOS25_12
SB_LVCMOS18_10
SB_SSTL18_HALF
SB_SSTL18_FULL
SB_LVCMOS33_8
SB_LVCMOS25_8
SB_LVCMOS25_4
SB_LVCMOS18_8
SB_LVCMOS18_4
SB_LVCMOS18_2
SB_LVCMOS15_4
SB_LVCMOS15_2
Attribute Name
SB_LVDS_INPUT
SB_MDDR10
SB_MDDR8
SB_MDDR4
SB_MDDR2
N/A
can
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