iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 109

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

Lattice Semiconductor Corporation
www.latticesemi.com
1.3
1.2
1.1
1.0
11-OCT-2008
31-MAY-2008
17-DEC-2008
4-SEPT-2008
minimum temperature to –40°C in
Added footprint and pinout information for the CS110 Wafer-Level Chip-Scale Ball Grid Array. Clarified that the
CB196 footprint shown is for the iCE65L04; the iCE65L08 footprint for the CB196 package is similar but
different. Added updated information on
Updated
standard. Corrected the diagram showing the direct differential clock input,
I/Os by package in
Updated I/O Bank 3 characteristics in
configuration to
Reset” section. Updated internal oscillator performance in and
58
Added information on CS63 and CB196 packages. Updated information on VPP_2V5 signal in
Reduced package height for CB1 2 and CB284 packages to 1.0 mm. Added
“Differential
Updated package roadmap (Table 2) and updated ordering codes (Figure 2). Updated Figure 7. Updated Figure
24. Added CS63 package footprint (Figure 36), pinout (Table 39) and Package.
Initial public release.
based on new oscillator timing. Completely reorganized the
Electrical Characteristics
Outputs” sections.
Table
Table 34.
20. Added pull-up resistor information in
Updated company address. Other minor updates throughout.
and
Figure 2
Table 7
AC Timing Guidelines
Differential Inputs and
and
and
Table
Table
48. Added NVCM programming temperature to
51. Corrected label in
sections. Added support for the LVCMOS15 I/O
Table
“Package and Pinout
Table 22
Outputs, including support for SubLVDS.
57. Updated configuration timing in
and
Figure 16.
“Differential
Figure
Figure
Information” section.
21. Added
(2.42, 30-MAR-2011)
14. Added JTAG
Updated the number of
Inputs” and
Table
“Internal Device
36.
Table
Table
109
48.