1894K-32LF IDT, 1894K-32LF Datasheet - Page 7

• Manufacturer Part Number: 1894K-32LF
• Description: Ethernet ICs 3.3V 10/100 PHY RMII
• Manufacturer: IDT

Specifications of 1894K-32LF

• Rohs: yes
• Part # Aliases: ICS1894K-32LF

The MIIM interface consists of the following:
•
•
MII Management Frame Format
Interrupt (INT)
P2/INT (pin 11) is an optional interrupt signal that is used to
inform the external controller that there has been a status
update in the ICS1894-32 PHY register. Register 23 shows
the status of the various interrupts while register 22 controls
the enabling/disabling of the interrupts.
MII Data Interface
The Media Independent Interface (MII) is specified in
Clause 22 of the IEEE 802.3u Specification. It provides a
common interface between physical layer and MAC layer
devices, and has the following key characteristics:
•
•
•
•
The ICS1894-32 is configured for MII mode upon power-up
or hardware reset with the following:
•
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Write
Read
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
A physical connection that incorporates the clock line
(MDC) and the data line (MDIO).
A specific protocol that operates across the
aforementioned physical connection that allows an
external controller to communicate with one or more
ICS1894-32 devices. Each ICS1894-32 device is
assigned a PHY address between 1 and 7 by the P[4:0]
strapping pins. P3 and P4 address bits are hardcoded to
‘0’ in design.
Supports 10Mbps and 100Mbps data rates.
Uses a 25MHz reference clock, sourced by the PHY.
Provides independent 4-bit wide (nibble) transmit and
receive data paths.
Contains two distinct groups of signals: one for
transmission and the other for reception.
A 25MHz crystal connected to REFIN, REFOUT (pins 30,
29), or an external 25MHz clock source (oscillator)
connected to REFIN
Preamble Start of
32 1’s
32 1’s
Frame
01
01
Read/Write
OP Code
10
01
PHY Address
Bits [4:0]
00AAA
00AAA
REG Address
•
The ICS1894-32 supports MIIM in both MII mode and RMII
mode.
The following table shows the MII Management frame
format for the ICS1894-32.
Bits [4:0]
RRRRR
RRRRR
An internal addressable set of thirty-one 8-bit MDIO
registers. Register [0:6] are required, and their functions
are defined by the IEEE 802.3u Specification. The
additional registers are provided for expanded
functionality.
7
TA
Z0
10
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
Data Bits
[15:0]
ICS1894-32
PHYCEIVER
REV M 021512
Idle
Z
Z