1894K-32LF IDT, 1894K-32LF Datasheet - Page 8

• Manufacturer Part Number: 1894K-32LF
• Description: Ethernet ICs 3.3V 10/100 PHY RMII
• Manufacturer: IDT

Specifications of 1894K-32LF

• Rohs: yes
• Part # Aliases: ICS1894K-32LF

MII Signal Definition
The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3u Specification for detailed information.
Transmit Clock (TXCLK)
TXCLK is sourced by the PHY. It is a continuous clock that
provides the timing reference for TXEN and TXD[3:0].
TXCLK is 2.5MHz for 10Mbps operation and 25MHz for
100Mbps operation.
Transmit Enable (TXEN)
TXEN indicates the MAC is presenting nibbles on TXD[3:0]
for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all
nibbles to be transmitted are presented on the MII, and is
negated prior to the first TXCLK following the final nibble of
a frame. TXEN transitions synchronously with respect to
TXCLK.
Transmit Data (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXCLK.
When TXEN is asserted, TXD[3:0] are accepted for
transmission by the PHY. TXD[3:0] is ”00” to indicate idle
when TXEN is de-asserted. Values other than “00” on
TXD[3:0] while TXEN is de-asserted are ignored by the
PHY.
Receive Clock (RXCLK)
RXCLK provides the timing reference for RXDV, RXD[3:0],
and RXER.
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
MII Signal Name
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
RXD[3:0]
TXD[3:0]
RXCLK
TXCLK
RXER
TXEN
RXDV
(with respect to PHY,
ICS1894-32 signal)
Direction
Output
Output
Output
Output
Output
Input
Input
Input
Output
Output
Input
Input
Input
Input, or (not required)
(with respect to MAC)
Direction
•
•
RXCLK is 2.5MHz for 10Mbps operation and 25MHz for
100Mbps operation.
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is
presenting recovered and decoded nibbles on RXD[3:0].
•
•
RXDV transitions synchronously with respect to RXCLK.
Receive Data (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC.
For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data from the PHY.
Receive Error (RXER)
RXER is asserted for one or more RXCLK periods to
indicate that an error (e.g. a coding error or any error that a
In 10Mbps mode, RXCLK is recovered from the line while
carrier is active. RXCLK is derived from the PHY’s
reference clock when the line is idle, or link is down.
In 100Mbps mode, RXCLK is continuously recovered
from the line. If link is down, RXCLK is derived from the
PHY’s reference clock.
In 10Mbps mode, RXDV is asserted with the first nibble of
the SFD (Start of Frame Delimiter), and remains asserted
until the end of the frame.
In 100Mbps mode, RXDV is asserted from the first nibble
of the preamble to the last nibble of the frame.
Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
Transmit Enable
Transmit Data [3:0]
Receive Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
Receive Data Valid
Receive Data [3:0]
Receive Error
8
Description
ICS1894-32
PHYCEIVER
REV M 021512