1894KI-40LF IDT, 1894KI-40LF Datasheet
1894KI-40LF
Specifications of 1894KI-40LF
Related parts for 1894KI-40LF
1894KI-40LF Summary of contents
Page 1
... For full/half duplex RMII only interface support, please refer to ICS1894-43 datasheet. — For full/half duplex MII only interface support, please refer to ICS1894-44 datasheet. — ICS1894-43 and ICS1894-44 are pin-compatible with ICS1894-40. IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Features • ...
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... TP_BN Thermal Pad TP_BN TP_BP TP_BP VDD VDD TCSR TCSR VSS 11 VSS 11 40-pin MLF 40-pin MLF IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 100Base-T PCS PMA TP_PMD • Framer • Clock Recovery • CRS/COL • Link Monitor Detection • ...
Page 3
... IO/Ipu RXCLK9 27 NOD/ IO/Ipd RXER IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Pin Description AMDIX Enable Twisted pair port A (for either transmit or receive) positive signal Twisted pair port A (for either transmit or receive) negative signal 3.3V Power Supply Twisted pair port B (for either transmit or receive) negative signal Twisted pair port B (for either transmit or receive) positive signal 3 ...
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... RMII Tx Mode: The TXD[1:0] bits are synchronous with REFIN. For each clock period in which TX_EN is asserted, two bits of data are received by the PHY from the MAC. IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Pin Description 10M/100M select as input (during power on reset and hardware reset) ...
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... The ICS1894- ethernet PHYceiver. During data transmission, it accepts sequential nibbles/di-bits from the MAC (Media Access Control), converts them into a serial bit stream, encodes them, and transmits them over the medium IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE AMDIX enable 0 = AMDIX disable Hardware pin select enable ...
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... IDLE condition on the Link Segment. In the 100Base-TX mode, the ICS1894-40 transmit channel sends a continuous stream of scrambled ones to signify the IDLE IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE condition. Similarly, the ICS1894-40 receive channel continually monitors its data stream and looks for a pattern of scrambled ones ...
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... Contains two distinct groups of signals: one for transmission and the other for reception. The ICS1894-40 is configured for MII mode upon power-up IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE • A physical connection that incorporates the clock line (MDC) and the data line (MDIO). ...
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... TXD[3:0] while TXEN is de-asserted are ignored by the PHY. Receive Clock (RXCLK) RXCLK provides the timing reference for RXDV, RXD[3:0], and RXER. IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Direction (with respect to MAC) Input Transmit Clock (2.5MHz for 10Mbps; 25MHz for 100Mbps) ...
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... Provides independent 2-bit wide (di-bit) transmit and receive data paths. • Contains two distinct groups of signals: one for transmission and the other for reception. In RMII mode MHz reference clock is connected to REFIN(pin 30). IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 9 ICS1894-40 PHYCEIVER REV K 022412 ...
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... That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are detected carrier is said to be detected. IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Direction (with respect to MAC) Input or Output ...
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... TP_BP & TP_BN cross transmit = TP_BP & TP_BN receive = TP_AP & TP_AN IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE AMDIX_EN (Pin 18) AMDIX enable pin with 20 kOhm pull-up resistor AMDIX_EN [19:9] MDIO register 19h bit 9 MDI_MODE [19:8] MDIO register 19h bit 8 ...
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... ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1 and 24.2.3.4. The ICS1894-40 supports two clock source configurations: a CMOS oscillator or a CMOS driver. The input to REFIN is CMOS (10% to 90% VDD), not TTL. Alternately, a 25MHz crystal may be used. IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE TPLL TX_STRUCTURE RX and OUT ...
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... ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Crystal or Oscillator Connection MII w/ Crystal Input MII w/ Oscillator Input RMII w/ Oscillator Input IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE ICS1894-40 REF_OUT REF_IN 36 25.000MHz 25 pF ICS1894-40 REF_OUT Ohm (optional) CMOS 25.000 ...
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... PHY status by providing signals that are intended for driving LEDs. Configuration is set by Bank0 Register 20. IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Once the exact value of load capacitance is established it will be the same for all boards using the same specification crystal ...
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... P3/RXD2 latched high) 38 The above circuit decodes the PHY address = 17 IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 3. The P0/LED0 and P1/ISO/LED1 pins must be pulled either up or down with an external resistor to establish the address of the ICS1894-40. The P2/INT, P3/RXD2 and P4/LED2 pins have internal pull-up/ pull-down resistors ...
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... IEEE reserved 0.3 IEEE reserved 0.2 IEEE reserved 0.1 IEEE reserved 0.0 IEEE reserved IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Register Name When Bit = 0 When Bit = 1 No effect Reset mode Disable Loopback mode Enable Loopback mode 10 Mbps operation 100 Mbps operation Disable Auto-Negotiation Enable Auto-Negotiation ...
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... OUI bit 2.7 OUI bit 2.6 OUI bit 2.5 OUI bit 2.4 OUI bit IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE When Bit = 0 When Bit = 1 Always 0. (Not N/A supported.) Mode not supported Mode supported Mode not supported Mode supported ...
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... Revision Number bit 2 3.1 Revision Number bit 1 3.0 Revision Number bit 0 Auto-Negotiation Advertisement Register 4 - 4.15 Next Page 4.14 IEEE reserved 4.13 Remote fault 4.12 IEEE reserved 4.11 IEEE reserved 4.10 IEEE reserved 4.9 100Base-T4 4.8 100Base-TX, full duplex IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE When Bit = 0 When Bit = 1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ...
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... Selector Field bit S4 5.3 Selector Field bit S3 5.2 Selector Field bit S2 5.1 Selector Field bit S1 5.0 Selector Field bit S0 IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE When Bit = 0 When Bit = 1 Advertise ability Do not advertise ability Advertise ability Do not advertise ability Advertise ability IEEE 802.3-specified ...
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... Message Page 7.12 Acknowledge 2 7.11 Toggle 7.10 Message code field /Unformatted code field 7.9 Message code field /Unformatted code field 7.8 Message code field /Unformatted code field IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE When Bit = 0 When Bit = 1 Always 0 N/A Always 0 N/A Always 0 N/A Always 0 N/A Always 0 N/A Always 0 ...
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... Message code field /Unformatted code field 8.4 Message code field /Unformatted code field IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE When Bit = 0 When Bit = 1 Bit value depends on the Bit value depends on the particular message particular message Bit value depends on the ...
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... Duplex 17.13 Auto-Negotiation Progress Monitor Bit 2 17.12 Auto-Negotiation Progress Monitor Bit 1 IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE When Bit = 0 When Bit = 1 Bit value depends on the Bit value depends on the particular message particular message Bit value depends on the Bit value depends on the ...
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... TM_SWITCH 18.7 IDT reserved 18.6 IDT reserved 18.5 Jabber inhibit 18.4 IDT reserved IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE When Bit = 0 When Bit = 1 Reference Decode Table Reference Decode Table Valid signal Signal lost PLL locked PLL failed to lock Normal Carrier or Idle False Carrier ...
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... Automatic 100Base-TX Power Down 20 - Extended Control Register Register 20.15 Str_enhance 20.14 Fast-off 20.13 LED4 mode 20.12 IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE When Bit = 0 When Bit = 1 Polarity automatically Polarity not automatically corrected corrected Normal SQE test SQE test disabled behavior Normal Link Loss ...
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... Interrupt flag read clear enable 22.13 Interrupt polarity 22.12 Interrupt flag auto clear enable IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE When Bit = 0 When Bit = 1 000 = Link Integrity 001 = activity/no activity 010 = Transmit Data 011 = Receive Data 100 = Collision 101 = 100/10 mode ...
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... Jabber Interrupt 23.6 Receive Error Interrupt 23.5 Page Receive Interrupt 23.4 Parallel Detect Fault Interrupt IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE When Bit = 0 When Bit = 1 Interrupt flag always Interrupt flag remains cleared when write 1 to unchanged when flag bit interrupt condition exists when written to flag bit ...
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... RX 100 DPD Enable 24.5 Admix_TX DPD Enable 24.4 Cdr100_cdr DPD Enable don't power down in DPD 24.3:0 Reserved IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE When Bit = 0 When Bit = 1 Link Partner Link Partner Acknowledge Acknowledge did not occurred occur Link Down did not occur ...
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... L = Latched on power-up/hardware reset † As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits. IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE When Bit = 0 When Bit = 1 ...
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... Stresses above the ratings listed below can cause permanent damage to the ICS1894-40. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. ...
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... The 18.2K resistor provides negative feedback to compensate for VDD changes. Reducing the value of this resistor will lower the 100baseT amplitude. Reducing the value of the resistor to ground on the other hand will increase the output signal amplitude. IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Minimum Typical – ...
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... Power Down (Reg0: Deep Power Down Current Consumption Table Register 24:8 Register 24:7 TPLL_100 DPD Enable Register 24:6 RX_100 DPD Enable Register 24:5 Admix_TX DPD Enable Register 24:4 CDR100_cdr DPD Enable Current (mA) (typical) IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE VDDIO (V) VDD and VDDD (V) 3.3 3.3 1.8 3.3 3.3 3.3 3.3 3.3 3.3 3 ...
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... Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage For 1.8 V Signals Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Symbol Conditions Min. Max. Units V 2 – IL ...
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... Timing Diagram figure shows the timing diagram for the time periods. Time Parameter Period t1 REF_IN Duty Cycle (MII) t2 REF_IN Period (MII) t1 REF_IN Duty Cycle (RMII) t2 REF_IN Period (RMII) REF_IN Timing Diagram REF_IN IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Symbol Min. Max. V 2.97 – – 0.33 IL Conditions Min. ...
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... Period t1 RXCLK Duty Cycle t2a RXCLK Period t2b RXCLK Period Receive Clock Timing Diagram t1 RXCLK IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Conditions – 100M MII (100Base-TX) 10M MII (10Base-T) t1 t2x Conditions – 100M MII (100Base-TX) 10M MII (10Base-T) t2 Min ...
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... The 10M MII Synchronous Transmit Timing Diagram figure shows the timing diagram for the time periods. Time Period t1 TXD[3:0], TXEN, TXER Setup to TXCLK Rise t2 TXD[3:0], TXEN, TXER Hold after TXCLK Rise IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Parameter Conditions t1 t2 Parameter Conditions Min ...
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... Period t1 RXD[3:0], RXDV, and RXER Setup to RXCLK Rise t2 RXD[3:0], RXDV, and RXER Hold after RXCLK Rise MII Interface: Synchronous Receive Timing RXCLK RXD[3:0] RXDV RXER IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE t1 t2 Parameter PHYCEIVER Min. Typ. Max. Units 10.0 – ...
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... MDC Rise Time to MDIO Valid t5 MDIO Setup Time to MDC t6 MDIO Hold Time after MDC MII Management Interface Timing Diagram MDC t1 MDIO (Output) MDC MDIO (Input) IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Parameter Conditions Min. Typ. Max. Units – 160 – ...
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... Period t1 First Bit of /5/ on TP_RX to /5/D/ on RXD 10M MII Receive Latency Timing Diagram † TP_RX RXCLK RXD 5 † Manchester encoding is not shown. IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Parameter Conditions Min. Typ. Max 10M MII – 6 ...
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... Period t1 TXD Sampled to MDI Output of First Bit 10M MII Transmit Latency Timing Diagram TXEN TXCLK TXD † TP_TX † Manchester encoding is not shown. IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Parameter Conditions Min. Typ. Max. 10M MII – 1.2 2 ...
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... The IEEE maximum is 18 bit times. MII/100M Stream Interface Transmit Latency Timing Diagram TXEN TXCLK TXD Preamble /J/ † TP_TX † Shown unscrambled. IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Conditions MII mode Preamble /K/ t1 Min. Typ. Max. – 2 ...
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... Time Period t1 TXEN Sampled Asserted to CRS Assert t2 TXEN De-Asserted to CRS De-Asserted 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) TXEN TXCLK CRS t1 IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Parameter Conditions t2 Min. Typ. Max ...
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... Time Period t1 TXEN Asserted to CRS Assert t2 TXEN De-Asserted to CRS De-Asserted 10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) TXEN TXCLK CRS t1 IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Parameter Conditions t2 Min. Typ. Max. 0 – ...
Page 43
... First Bit of /J/ into TP_RX to /J/ on RXD 100M MII/100M Stream Interface: Receive Latency Timing Diagram † TP_RX RXCLK RXD † Shown unscrambled. IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Conditions Min. Typ. Max. 100M MII t1 43 PHYCEIVER Units – ...
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... The IEEE minimum is 13 bit times, and the maximum is 24 bit times. 100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram First bit † TP_RX CRS COL † Shown unscrambled. IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Parameter Conditions Half-Duplex Mode Half-Duplex Mode t1 t2 Min. Typ. Max. – 10 – ...
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... The Power-On Reset Timing Diagram shows the timing diagram for the time periods. Time Period VDD ≥ 2 Reset Complete t1 Power-On Reset Timing Diagram 2.7 V VDD TXCLK Valid IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Parameter Conditions t1 Min. Typ. Max. Units – ...
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... Minimum RESETn Pulse Width t3 RESETn Released to TXCLK Valid Hardware Reset and Power-Down Timing Diagram REF_IN RESETn TXCLK Valid Power Consumption (AC only) IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Parameter t1 t2 Conditions Min. Typ. Max – – 60 – 200 – ...
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... Period t1 COL Heartbeat Assertion Delay from TXEN De-Assertion t2 COL Heartbeat Assertion Duration 10Base-T Heartbeat (SQE) Timing Diagram TXEN TXCLK COL IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Conditions Min. 10Base-T Half Duplex 10Base-T Half Duplex PHYCEIVER Typ. Max. Units – ...
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... Note: For more information on 10Base-T jabber operations, see the section, “10Base-T Operation: Jabber”. Time Parameter Period t1 Jabber Activation Time t2 Jabber De-Activation Time 10Base-T Jabber Timing Diagram TXEN TP_TX COL IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Conditions 10Base-T Half Duplex 10Base-T Half Duplex t1 Min. Typ. Max. Units 20 – 35 300 – ...
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... Time Period t1 Normal Link Pulse Width t2 Normal Link Pulse to Normal Link Pulse Period 10Base-T Normal Link Pulse Timing Diagram TP_TXP t1 IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Parameter Conditions t2 Min. Typ. Max. Units 10Base-T – 100 – 10Base-T ...
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... Number of Clock/Data Pulses in a Burst Auto-Negotiation Fast Link Pulse Timing Diagram Clock Pulse Differential Twisted Pair t1 Transmit Signal FLP Burst Differential Twisted Pair Transmit Signal IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Parameter Data Pulse Conditions Min. Typ. Max. ...
Page 51
... Hold time Transmit Timing REFCLK TX_EN TXD[1:0] Marking Diagram (industrial) ICS 1894KI40L YYWW ORIGIN ###### Notes: 1. “L” or “LF” designates Pb (lead) free, RoHS compliant. 2. “I” designates industrial temperature range. 3. ‘YYWW’ designates date code. 4. ‘ORIGIN’ desigantes counrty of origin. 5. ‘######’ desigantes the lot number. ...
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... Ordering Information Part / Order Number Marking 1894KI-40LF see page 51 1894KI-40LFT 1894K-40LF see page 51 1894K-40LFT "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...
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... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners ...