1894KI-40LF IDT, 1894KI-40LF Datasheet - Page 15

• Manufacturer Part Number: 1894KI-40LF
• Description: Ethernet ICs 3.3V 10/100 PHY RMII
• Manufacturer: IDT

Specifications of 1894KI-40LF

• Rohs: yes
• Part # Aliases: ICS1894KI-40LF

Pins for Monitoring the Data Link table
Note:
1. During either power-on reset or hardware reset, each
multi-function configuration pin is an input that is sampled
when the ICS1894-40 exits the reset state. After sampling is
complete, these pins are output pins that can drive status
LEDs.
2. A software reset does not affect the state of a
multi-function configuration pin. During a software reset, all
multi-function configuration pins are outputs.
The following figure shows typical biasing and LED connections for the ICS1894-40.
The above circuit decodes the PHY address = 17
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
P0/LED0
P1/ISO/LED1
P4/LED2
LED3
SI/LED4
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Pin
P4/LED2
(always
latched high)
38
Link, Activity, Tx, Rx, COL, Mode, Dplx
Link, Activity, Tx, Rx, COL, Mode, Dplx
Link, Activity, Tx, Rx, COL, Mode, Dplx
Link, Activity, Tx, Rx, COL, Mode, Dplx
Link, Activity, Tx, Rx, COL, Mode, Dplx
LED Driven by the Pin’s Output Signal
P3/RXD2
19
P2/INT
12
ICS1894-40
3. The P0/LED0 and P1/ISO/LED1 pins must be pulled
either up or down with an external resistor to establish the
address of the ICS1894-40. The P2/INT, P3/RXD2 and
P4/LED2 pins have internal pull-up/ pull-down resistors.
LEDs may be placed in series with these resistors to provide
a designated status indicator as described in the Pins for
Monitoring the Data Link table. Use 1KΩ resistors.
Caution: Pins listed in the Pins for Monitoring the Data Link
table must not float.
4. As outputs, the asserted state of a multi-function
configuration pin is the inverse of the sense sampled during
reset. This inversion provides a signal that can illuminate an
LED during an asserted state. For example, if a
multi-function configuration pin is pulled down to ground
through an LED and a current-limiting resistor, then the
sampled sense of the input is low. To illuminate this LED for
the asserted state, the output is driven high.
5. Adding 10KΩ resistors across the LEDs ensures the PHY
address is fully defined during slow VDD power-ramp
conditions.
LED1
P1/ISO/LED1
15
40
10KΩ
1KΩ
P0/LED0
39
LED0
ICS1894-40
VDD
10KΩ
1KΩ
PHYCEIVER
REV K 022412