KSZ8851-16MLLU Micrel, KSZ8851-16MLLU Datasheet - Page 58

• Manufacturer Part Number: KSZ8851-16MLLU
• Description: Ethernet ICs Single-Port Ethernet Controller (Automotive Grade)
• Manufacturer: Micrel

Specifications of KSZ8851-16MLLU

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

Interrupt Status Register (0x92 – 0x93): ISR
This register contains the status bits for all QMU and other interrupt sources.
When the corresponding enable bit is set, it causes the interrupt pin to be asserted.
This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register
bits are not cleared when read. The user has to write “1” to clear.
May 2012
Micrel, Inc.
Bit
11
10
9
8
7
6
5
4
3
2
1
0
Bit
15
14
13
Default Value
Default Value
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
(W1C)
(W1C)
(W1C)
R/W
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
Description
RXOIE Receive Overrun Interrupt Enable
When this bit is set, the Receive Overrun interrupt is enabled.
When this bit is reset, the Receive Overrun interrupt is disabled.
Reserved
TXPSIE Transmit Process Stopped Interrupt Enable
When this bit is set, the Transmit Process Stopped interrupt is enabled.
When this bit is reset, the Transmit Process Stopped interrupt is disabled.
RXPSIE Receive Process Stopped Interrupt Enable
When this bit is set, the Receive Process Stopped interrupt is enabled.
When this bit is reset, the Receive Process Stopped interrupt is disabled.
Reserved
TXSAIE Transmit Space Available Interrupt Enable
When this bit is set, the Transmit memory space available interrupt is enabled.
When this bit is reset, the Transmit memory space available interrupt is disabled.
RXWFDIE Receive Wake-up Frame Detect Interrupt Enable
When this bit is set, the Receive wakeup frame detect interrupt is enabled.
When this bit is reset, the Receive wakeup frame detect interrupt is disabled.
RXMPDIE Receive Magic Packet Detect Interrupt Enable
When this bit is set, the Receive magic packet detect interrupt is enabled.
When this bit is reset, the Receive magic packet detect interrupt is disabled.
LDIE Linkup Detect Interrupt Enable
When this bit is set, the wake-up from linkup detect interrupt is enabled.
When this bit is reset, the linkup detect interrupt is disabled.
EDIE Energy Detect Interrupt Enable
When this bit is set, the wake-up from energy detect interrupt is enabled.
When this bit is reset, the energy detect interrupt is disabled.
Reserved.
DEDIE Delay Energy Detect Interrupt Enable
When this bit is set, the delay energy detect interrupt is enabled.
When this bit is reset, the delay energy detect interrupt is disabled.
Note: the delay energy detect interrupt till device is ready for host access.
Description
LCIS Link Change Interrupt Status
When this bit is set, it indicates that the link status has changed from link up to link down,
or link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
TXIS Transmit Interrupt Status
When this bit is set, it indicates that the TXQ MAC has transmitted at least a frame on the
MAC interface and the QMU TXQ is ready for new frames from the host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXIS Receive Interrupt Status
When this bit is set, it indicates that the QMU RXQ has received at least a frame from the
MAC interface and the frame is ready for the host CPU to process.
58
KSZ8851-16MLL/MLLI
M9999-050112-2.1