KSZ8851-16MLLU Micrel, KSZ8851-16MLLU Datasheet - Page 6

• Manufacturer Part Number: KSZ8851-16MLLU
• Description: Ethernet ICs Single-Port Ethernet Controller (Automotive Grade)
• Manufacturer: Micrel

Specifications of KSZ8851-16MLLU

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

Micrel, Inc.
KSZ8851-16MLL/MLLI
Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3.............................................................49
0x5C – 0x5F: Reserved ..............................................................................................................................49
Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0 .....................................................................49
Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1 .....................................................................49
Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0 .............................................................50
Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1 .............................................................50
Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2 .............................................................50
Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3.............................................................50
0x6C – 0x6F: Reserved ..............................................................................................................................50
Transmit Control Register (0x70 – 0x71): TXCR ........................................................................................50
Transmit Status Register (0x72 – 0x73): TXSR ..........................................................................................51
Receive Control Register 1 (0x74 – 0x75): RXCR1 ....................................................................................51
Receive Control Register 2 (0x76 – 0x77): RXCR2 ....................................................................................53
TXQ Memory Information Register (0x78 – 0x79): TXMIR .........................................................................53
0x7A – 0x7B: Reserved ..............................................................................................................................53
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR ............................................................53
Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR...................................................54
TXQ Command Register (0x80 – 0x81): TXQCR .......................................................................................55
RXQ Command Register (0x82 – 0x83): RXQCR ......................................................................................55
TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR .........................................................................56
RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR ........................................................................56
0x88 – 0x8B: Reserved...............................................................................................................................57
RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR ..............................................................57
RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR .........................................................57
Interrupt Enable Register (0x90 – 0x91): IER .............................................................................................57
Interrupt Status Register (0x92 – 0x93): ISR ..............................................................................................58
0x94 – 0x9B: Reserved...............................................................................................................................59
RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR .............................................................59
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR ................................................................60
MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0.................................................................60
MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1.................................................................60
MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2.................................................................60
MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3.................................................................60
0xA8 – 0xAF: Reserved ..............................................................................................................................61
Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR.................................................................61
Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR ...............................................................61
Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR..........................................................61
0xB6 – 0xBF: Reserved ..............................................................................................................................61
Chip ID and Enable Register (0xC0 – 0xC1): CIDER .................................................................................61
0xC2 – 0xC5: Reserved..............................................................................................................................61
Chip Global Control Register (0xC6 – 0xC7): CGCR .................................................................................62
Indirect Access Control Register (0xC8 – 0xC9): IACR ..............................................................................62
0xCA – 0xCF: Reserved .............................................................................................................................62
Indirect Access Data Low Register (0xD0 – 0xD1): IADLR ........................................................................62
Indirect Access Data High Register (0xD2 – 0xD3): IADHR .......................................................................62
Power Management Event Control Register (0xD4 – 0xD5): PMECR........................................................63
Go-Sleep & Wake-Up Time Register (0xD6 – 0xD7): GSWUTR ................................................................64
PHY Reset Register (0xD8 – 0xD9): PHYRR .............................................................................................64
May 2012
6
M9999-050112-2.1