1893AFILFT IDT, 1893AFILFT Datasheet - Page 119
![no-image](/images/no-image-200.jpg)
1893AFILFT
Manufacturer Part Number
1893AFILFT
Description
Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
Manufacturer
IDT
Datasheet
1.1893AFLF.pdf
(136 pages)
Specifications of 1893AFILFT
Rohs
yes
Part # Aliases
ICS1893AFILFT
- Current page: 119 of 136
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10.5.6 100M/MII Media Independent Interface: Synchronous Receive Timing
ICS1893AF, Rev. D 10/26/04
RXCLK
RXD[3:0]
RXDV
RXER
Table 10-13
timing. The time periods consist of timings of signals on the following pins:
•
•
•
•
Figure 10-7
Table 10-13. MII Interface: Synchronous Receive Timing
Figure 10-7. MII Interface Synchronous Receive Timing Diagram
Period
Time
RXCLK
RXD[3:0]
RXDV
RXER
ICS1893AF Data Sheet - Release
t1
t2
RXD[3:0], RXDV, and RXER Setup to RXCLK Rise
RXD[3:0], RXDV, and RXER Hold after RXCLK Rise
shows the timing diagram for the time periods.
lists the significant time periods for the MII / 100M Stream Interface synchronous receive
Copyright © 2004, Integrated Circuit Systems, Inc.
Parameter
t1
All rights reserved.
119
t2
Chapter 10 DC and AC Operating Conditions
Min.
10.0
10.0
Typ.
–
–
Max.
October, 2004
–
–
Units
ns
ns
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