PCA9554ATS-T NXP Semiconductors, PCA9554ATS-T Datasheet
PCA9554ATS-T
Specifications of PCA9554ATS-T
Related parts for PCA9554ATS-T
PCA9554ATS-T Summary of contents
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... The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I were developed to enhance the NXP Semiconductors family of I The improvements include higher drive capability I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, and so on ...
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... Ordering information Table 1. Ordering information Type number Topside marking PCA9554D PCA9554D PCA9554AD PCA9554AD PCA9554DB 9554DB PCA9554ADB 9554A PCA9554TS PCA9554 PCA9554ATS PA9554A PCA9554PW 9554DH [1] PCA9554PW/Q900 9554DH PCA9554APW 9554ADH PCA9554BS 9554 PCA9554ABS 554A PCA9554BS3 P54 PCA9554ABS3 54A ...
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... NXP Semiconductors Table 2. Ordering options …continued Type number Orderable part number PCA9554ADB PCA9554ADB,112 PCA9554ADB,118 PCA9554TS PCA9554TS,112 PCA9554TS,118 PCA9554ATS PCA9554ATS,112 PCA9554ATS,118 PCA9554PW PCA9554PW,112 PCA9554PW,118 PCA9554PW/Q900 PCA9554PW/Q900,118 TSSOP16 Reel 13” Q1/T1 PCA9554APW PCA9554APW,112 PCA9554APW,118 PCA9554BS PCA9554BS,118 PCA9554ABS PCA9554ABS,118 PCA9554BS3 PCA9554BS3,118 PCA9554ABS3 PCA9554ABS3,118 PCA9554U PCA9554U,029 ...
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... NXP Semiconductors 4. Block diagram SCL SDA Fig 1. PCA9554_9554A Product data sheet PCA9554/PCA9554A INPUT 2 I C-BUS/SMBus FILTER POWER-ON RESET All I/Os are set to inputs at reset. Block diagram of PCA9554/PCA9554A All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 PCA9554 ...
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... PCA9554DB PCA9554ADB IO1 5 6 IO2 7 IO3 Fig 3. Pin configuration for SSOP16 INT 1 SCL 2 3 n.c. 4 SDA V 5 PCA9554TS DD PCA9554ATS n. IO0 10 Fig 5. Pin configuration for SSOP20 PCA9554BS3 PCA9554ABS3 terminal 1 index area IO0 3 IO1 4 IO2 Transparent top view Fig 7. ...
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... NXP Semiconductors 5.2 Pin description Table 3. Symbol IO0 IO1 IO2 IO3 V SS IO4 IO5 IO6 IO7 INT SCL SDA V DD n.c. [1] HVQFN16 package die supply ground is connected to both V be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board ...
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... NXP Semiconductors 6.1.2 Register 0 - Input Port register This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default ‘X’ is determined by the externally applied logic level, normally ‘1’ when no external signal externally applied because of the internal pull-up resistors ...
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... NXP Semiconductors 6.1.4 Register 2 - Polarity Inversion register This register allows the user to invert the polarity of the Input Port register data bit in this register is set (written with ‘1’), the corresponding Input Port data is inverted bit in this register is cleared (written with a ‘0’), the Input Port data polarity is retained. ...
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... NXP Semiconductors 6.3 Interrupt output The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input Port register is read. Note that changing an I/O from and output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register ...
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... NXP Semiconductors 6.5 Device address Fig 9. 6.6 Bus transactions Data is transmitted to the PCA9554/PCA9554A registers using the Write mode as shown in Figure 11 Read mode as shown in auto-increment function, so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent ...
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... NXP Semiconductors slave address SDA START condition acknowledge slave address (cont (repeated) START condition Fig 13. Read from register SCL slave address SDA START condition read from port ...
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... NXP Semiconductors 7. Application design-in information kΩ MASTER CONTROLLER SCL SDA INT V SS Device address configured as 0100 100X for this example. IO0, IO1, IO2 configured as outputs. IO3, IO4, IO5 configured as inputs. IO6 and IO7 are not used and must be configured as outputs. ...
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... NXP Semiconductors 9. Static characteristics Table 10. Static characteristics Symbol Parameter Supplies V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current ...
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... NXP Semiconductors Table 10. Static characteristics Symbol Parameter Select inputs A0, A1 LOW-level input voltage IL V HIGH-level input voltage IH I input leakage current LI must be lowered to 0.2 V for at least 5 s in order to reset part. [ [2] Each I/O must be externally limited to a maximum and the device must be limited to a maximum current of 100 mA. ...
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... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 16. Definition of timing PCA9554_9554A Product data sheet HD;DAT HIGH SU;DAT All information provided in this document is subject to legal disclaimers. Rev. 9 — 19 March 2013 PCA9554; PCA9554A 2 8-bit I C-bus and SMBus I/O port with interrupt ...
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... NXP Semiconductors 11. Package outline SO16: plastic small outline package; 16 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 18 ...
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... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.4 mm 1.5 0.25 0 1.2 Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION IEC SOT266-1 Fig 19 ...
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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 12. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 13.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA9554_9554A Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 14. Soldering: PCB footprints Footprint information for reflow soldering of SO16 package solder land occupied area DIMENSIONS 1.270 1.320 11.200 6.400 2.400 Fig 24. PCB footprint for SOT162-1 (SO16); reflow soldering PCA9554_9554A Product data sheet (4x) ...
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... NXP Semiconductors Footprint information for reflow soldering of TSSOP16 package solder land occupied area DIMENSIONS 0.650 0.750 8.600 5.400 1.600 Fig 25. PCB footprint for SOT338-1 (HVQFN16); reflow soldering PCA9554_9554A Product data sheet (4x) P1 Generic footprint pattern ...
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... NXP Semiconductors Footprint information for reflow soldering of SSOP20 package Hy Gy solder land occupied area DIMENSIONS 0.650 0.750 7.200 4.500 1.350 Fig 26. PCB footprint for SOT266-1 (SSOP20); reflow soldering PCA9554_9554A Product data sheet (4x ...
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... NXP Semiconductors Footprint information for reflow soldering of TSSOP16 package solder land occupied area DIMENSIONS 0.650 0.750 7.200 4.500 1.350 Fig 27. PCB footprint for SOT403-1 (TSSOP16); reflow soldering PCA9554_9554A Product data sheet (4x) P1 Generic footprint pattern ...
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... NXP Semiconductors Footprint information for reflow soldering of HVQFN16 package (0.105 solder land solder paste deposit solder land plus solder paste occupied area Dimensions 0.650 5.000 5.000 2.800 2.800 07-05-07 Issue date 09-06-15 Fig 28. PCB footprint for SOT629-1 (HVQFN16); reflow soldering ...
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... NXP Semiconductors Footprint information for reflow soldering of HVQFN16 package (0.105 solder land solder paste deposit solder land plus solder paste occupied area Dimensions 0.50 4.00 4.00 2.20 2.20 12-03-07 Issue date 12-03-08 Fig 29. PCB footprint for SOT758-1 (HVQFN16); reflow soldering PCA9554_9554A Product data sheet ...
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... NXP Semiconductors 15. Abbreviations Table 14. Acronym ACPI CDM CMOS ESD FET GPIO HBM 2 I C-bus I/O LED MM PCB POR SMBus PCA9554_9554A Product data sheet 8-bit I Abbreviations Description Advanced Configuration and Power Interface Charged Device Model Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Field-Effect Transistor General Purpose Input/Output ...
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... NXP Semiconductors 16. Revision history Table 15. Revision history Document ID Release date PCA9554_9554A v.9 20130319 • Modifications: Removed DIP16 package option (type numbers PCA9554N and PCA9554AN) • Added • Deleted (old) Figure 2, “Pin configuration for DIP16” • Figure 10 “PCA9554A device address” “hardware selectable” ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.1.1 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.1.2 Register 0 - Input Port register . . . . . . . . . . . . . 7 6.1.3 Register 1 - Output Port register 6.1.4 Register 2 - Polarity Inversion register . . . . . . . 8 6 ...