ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 41

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
R27 (1Bh)
Power Management
(2)
Note: A value of “1” indicates the output is enabled; a value of ‘0’ disables the output.
Register Address
3.15.1. Audio Output Control
3.15.2. Headphone Switch
See Power management section. The output enable bits are also power management bits and the
outputs will be turned off when disabled.
The HPDETECT pin is used to detect connection of a headphone. When headphone insertion is
detected, the codec can automatically disable the speaker outputs and enable the headphone out-
puts. Control bits determine the meaning and polarity of the input.
In addition to enabling and disabling outputs, the EQ may also be controlled using the HP_DET pin.
The 2 EQ filters may be configured so that one EQ is active when the Headphone output is active
and the other EQ is active when the Speaker output is active (independent HP and Speaker EQ).
One EQ may be enabled only when the Speaker is active and the other EQ may be on when either
of the outputs are active (Speaker compensation and USER EQ) or other combinations are possible.
Note that the EQ coefficients must be programmed and the EQs must be enabled using their control
registers. The HP_DET logic can only disable the EQ filters.
Bit
7
6
5
4
3
2
1
0
SPKOutR
SPKOutL
HPOutR
HPOutL
RSVD
RSVD
VREF
Label
D2S
Table 47. Power Management 2 Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
41
0
0
0
0
0
0
0
1
Analog in D2S AMP Enable
Left Headphone Output Enable
Right Headphone Output Enable
Left Speaker Output Enable
Right Speaker Output Enable
Voltage reference
Description
ACS422X68
V1.6 01/13