ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 62

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ACS422A68TAGZBX8

Manufacturer Part Number
ACS422A68TAGZBX8
Description
Interface - CODECs
Manufacturer
IDT
Datasheet

Specifications of ACS422A68TAGZBX8

Rohs
yes
Part # Aliases
IDTACS422A68TAGZBX8
ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
5. DIGITAL AUDIO AND CONTROL INTERFACES
5.1.
For digital audio data, the ACS422x68 uses five pins to input and output digital audio data.
The clock signals ADCBCLK, ADCLRCK, DACBCLK, and DACLRCK are outputs when the ACS422x68 operates as a
master; they are inputs when it is a slave. Three different data formats are supported:
All of these modes are MSB first.
5.2.
The ACS422x68 can be used as either a master or slave device, selected by the MS Bit. When operating as a master,
the ACS422x68 generates ADCBCLK, ADCLRCLK, DACBCLK and DACLRCLK and controls sequencing of the data
transfer the data pins. In slave mode, the ACS422x68 provides data aligned to clocks it receives.
Data Interface
Master and Slave Mode Operation
CODEC
CODEC
ADCDOUT: ADC data output
ADCLRCK: ADC data alignment clock
ADCBCLK: Bit clock, for synchronization
DACDIN: DAC data input
DACLRCK: DAC data alignment clock
DACBCLK: Bit clock, for synchronization
Left justified
Right justified
I
2
S
ADCLRCLK
DACLRCLK
ADCLRCLK
DACLRCLK
ADCDOUT
ADCDOUT
ADCBCLK
DACBCLK
ADCBCLK
DACBCLK
DACDIN
DACDIN
Figure 24. Master mode
Figure 25. Slave mode
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ENCODER/
ENCODER/
DECODER
DECODER
DSP
DSP
ACS422X68
V1.6 01/13

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