ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 67

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
5.8.
The default master mode bit clock generator automatically produces a bit clock frequency based on the sample rate
and word length. When enabled by setting the appropriate BCM bits, the bit clock mode (BCM) function overrides the
default master mode bit clock generator to produce the bit clock frequency shown below: Note that selecting a word
length of 24-bits in Auto mode generates 64 clocks per frame (64fs)
3.ADC (record path) is off when ADCL, and ADCR power states are off (PGA, D2S, Boost power states are not
considered.)
R21 (15h)
Audio Interface
Control 3
(AIC3)
Register Address
5.7.5.
5.7.6.
Bit Clock Mode
Tri-state (TRI)
ADC Output Pin State
Audio Interface Control 3 Register
0
1
Bit
7:6
5
4
3
2
1
0
ADOPDD
DBCPDD
ABCPDD
DLRPDD
ALRPDD
DDIPDD
RSVD
Label
Record Path
Power State
Table 72. ADC Data Output pin state
On
NA
NA
Off
Off
Table 73. AIC3 Register
Type
RW
RW
RW
RW
RW
RW
R
Default
67
Pull-down (ADOPDD)
0
0
0
0
0
0
0
ADC Data Out
Reserved
ADCDOUT Pull-Down Disable
0 = Pull-Down active when tri-stated or the ADC path
is powered down.
1 = Pull-Down always disabled
ADCLRCLK Pull-Down Disable
0 = Pull-Down active when configured as input
1 = Pull-Down always disabled
ADCBCLK Pull-Down Disable
0 = Pull-Down active when configured as input
1 = Pull-Down always disabled
DACDIN Pull-Down Disable
0 = Pull-Down active
1 = Pull-Down always disabled
DACLRCLK Pull-Down Disable
0 = Pull-Down active when configured as input
1 = Pull-Down always disabled
DACBCLK Pull-Down Disable
0 = Pull-Down active when configured as input
1 = Pull-Down always disabled
NA
0
1
0
1
Description
ADC Data Out
Off, pulled-low
Off, pulled-low
Off, floating
Off, floating
Active
State
ACS422X68
V1.6 01/13