PCA6416APW,118 NXP Semiconductors, PCA6416APW,118 Datasheet
PCA6416APW,118
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PCA6416APW,118 Summary of contents
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PCA6416A Low-voltage translating 16-bit I with interrupt output, reset, and configuration registers Rev. 2. — 10 January 2013 1. General description The PCA6416A is a 16-bit general purpose I/O expander that provides remote I/O expansion for most microcontroller families via ...
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... NXP Semiconductors INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I remain a simple slave device. The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while consuming low device current ...
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... PCA6416APW PCA6416A TSSOP24 3.1 Ordering options Table 2. Ordering options Type number Orderable part number PCA6416AEV PCA6416AEVJ PCA6416AHF PCA6416AHF,128 PCA6416APW PCA6416APW,118 4. Block diagram ADDR V DD(I2C-bus) V DD(P) RESET Fig 1. PCA6416A Product data sheet Low-voltage translating 16-bit I Description plastic very thin fine-pitch ball grid array package; 24 balls; ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning V DD(I2C-bus) RESET Fig 2. ball A1 index area Fig 4. PCA6416A Product data sheet Low-voltage translating 16-bit INT P0_0 4 21 P0_1 P0_2 PCA6416APW 7 18 P0_3 P0_4 8 17 P0_5 9 16 P0_6 P0_7 12 13 ...
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... NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin TSSOP24 HWQFN24 VFBGA24 INT DD(I2C-bus) RESET 3 24 [1] P0_0 4 1 [1] P0_1 5 2 [1] P0_2 6 3 [1] P0_3 7 4 [1] P0_4 8 5 [1] P0_5 9 6 [1] P0_6 10 7 [1] P0_7 [2] P1_0 13 10 [2] P1_1 14 11 [2] P1_2 ...
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... NXP Semiconductors 6. Voltage translation Table C-bus and the PCA6416A. Table 4. V DD(I2C-bus) 1.8 V 1.8 V 1.8 V 1.8 V 2.5 V 2.5 V 2.5 V 2.5 V 3.3 V 3.3 V 3 Functional description Refer to 7.1 Device address The address of the PCA6416A is shown in Fig 6. ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW (logic 0) to assign one of the two possible slave addresses ...
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... NXP Semiconductors 7.2 Interface definition Table 5. Byte 2 I C-bus slave address I/O data bus 7.3 Pointer register and command byte Following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the Pointer register in the PCA6416A. The lower three bits of this data byte state the operation (read or write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that will be affected ...
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... NXP Semiconductors 7.4 Register descriptions 7.4.1 Input port registers (00h, 01h) The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port registers are read only; writes to these registers have no effect. ...
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... NXP Semiconductors 7.4.3 Polarity inversion registers (04h, 05h) The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the Configuration register bit in these registers is set (written with ‘1’), the corresponding port pin’s polarity is inverted in the input register bit in this register is cleared (written with a ‘ ...
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... NXP Semiconductors 7.5 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above V 5 the I/O is configured as an output enabled, depending on the state of the Output port register. In this case, there are low-impedance paths between the I/O pin and either V recommended levels for proper operation ...
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... NXP Semiconductors 7.7 Reset input (RESET) The RESET input can be asserted to initialize the system while keeping the V operating level. A reset can be accomplished by holding the RESET pin LOW for a minimum of t changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O levels at the P port can be changed externally or through the master. This input requires a pull-up resistor ...
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SCL slave address AD SDA START condition R/W acknowledge from slave write to port data out from port 0 data ...
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... NXP Semiconductors 8.2 Read commands To read data from the PCA6416A, the bus master must first send the PCA6416A address with the least significant bit set to a logic 0 (see The command byte is sent after the address and determines which register accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1 ...
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INT t t v(INT) rst(INT) SCL R/W slave address I0.x AD SDA ...
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DATA 00 t h(D) data into port 1 DATA 10 INT t t v(INT) rst(INT) SCL R/W slave address I0.x AD SDA ...
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... NXP Semiconductors 9. Application design-in information V = 1.8 V DD(I2C-bus) 10 kΩ MASTER CONTROLLER SCL SDA INT RESET V SS Device address configured as 0100 000x for this example. P0_0 and P0_2 through P1_0 are configured as inputs. P0_1 and P1_1 through P1_7 are configured as outputs. ...
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... NXP Semiconductors Fig 15. High value resistor in parallel with 9.2 Power-on reset requirements In the event of a glitch or data corruption, PCA6416A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application ...
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... NXP Semiconductors Table 15. Recommended supply sequencing and ramp rates (unless otherwise noted). Not tested; specified by design. amb Symbol Parameter (dV/dt) fall rate of change of voltage f (dV/dt) rise rate of change of voltage r t reset delay time d(rst) V glitch supply voltage difference DD(gl) t supply voltage glitch pulse width ...
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... NXP Semiconductors 10. Limiting values Table 16. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter C-bus supply voltage DD(I2C-bus) V supply voltage port P DD(P) V input voltage I V output voltage O I input clamping current IK I output clamping current OK I input/output clamping current ...
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... NXP Semiconductors 12. Thermal characteristics Table 18. Thermal characteristics Symbol Parameter Z transient thermal impedance from junction to ambient th(j-a) [1] The package thermal impedance is calculated in accordance with JESD 51-7. 13. Static characteristics Table 19. Static characteristics + amb DD(I2C-bus) Symbol Parameter V input clamping voltage ...
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... NXP Semiconductors Table 19. Static characteristics + amb DD(I2C-bus) Symbol Parameter I input current I I HIGH-level input current IH I LOW-level input current IL I supply current DD I additional quiescent DD supply current C input capacitance i C input/output capacitance io [1] For I , all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3 ...
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... NXP Semiconductors 13.1 Typical characteristics (μ 5.5 V DD(P) 5 3.3 V 2 −40 − DD(I2C-bus) DD(P) Fig 21. Supply current versus ambient temperature = 25 C T amb DD(I2C-bus) DD(P) Fig 23. Supply current versus supply voltage PCA6416A Product data sheet Low-voltage translating 16-bit I ...
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... NXP Semiconductors 35 I sink (mA −40 °C amb 25 ° ° 0 1.65 V DD( sink (mA −40 °C amb 25 ° ° 0 2.5 V DD( sink (mA −40 °C 60 amb 25 °C 85 ° 0 5.0 V DD(P) Fig 24. I/O sink current versus LOW-level output voltage ...
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... NXP Semiconductors 30 I source (mA −40 °C amb 25 ° ° 0 1.65 V DD( source (mA −40 °C amb 25 ° ° 0 2.5 V DD( source T = −40 °C amb (mA) 25 °C 85 ° 0 5.0 V DD(P) Fig 25. I/O source current versus HIGH-level output voltage ...
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... NXP Semiconductors 120 V OL (mV) 100 ( (2) 40 (4) 20 (3) 0 −40 − DD(P) sink ( DD(P) sink ( 1 DD(P) sink ( DD(P) sink Fig 26. LOW-level output voltage versus temperature PCA6416A Product data sheet Low-voltage translating 16-bit I 002aah056 ...
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... NXP Semiconductors 14. Dynamic characteristics 2 Table 20. I C-bus interface timing requirements Over recommended operating free air temperature range, unless otherwise specified. See Symbol Parameter f SCL clock frequency SCL t HIGH period of the SCL clock HIGH t LOW period of the SCL clock LOW t pulse width of spikes that must ...
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... NXP Semiconductors Table 22. Switching characteristics Over recommended operating free air temperature range; C Symbol Parameter t valid time on pin INT v(INT) t reset time on pin INT rst(INT) t data output valid time v(Q) t data input set-up time su(D) t data input hold time h(D) 15. Parameter measurement information a. SDA load configuration ...
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... NXP Semiconductors a. Interrupt load configuration START condition slave address SDA SCL INT A t v(INT) A data into ADDRESS port INT t v(INT) Pn View Voltage waveforms C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z All parameters and waveforms are not applicable to all devices ...
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... NXP Semiconductors a. P port load configuration SCL SDA Pn b. Write mode (R SCL Pn c. Read mode (R includes probe and jig capacitance measured from 0.7 v(Q) All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time, with one transition per measurement. ...
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... NXP Semiconductors V DD(I2C-bus) SDA DUT a. SDA load configuration START SCL SDA RESET t rec(rst RESET timing C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time, with one transition per measurement. ...
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... NXP Semiconductors 16. Package outline HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 0.75 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0.30 mm 0.8 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors VFBGA24: plastic very thin fine-pitch ball grid array package; 24 balls; body 0.85 mm ball A1 index area ball index area Dimensions Unit max 1.00 0.25 0.75 0.35 mm nom 0.85 0.20 0.65 0.30 min 0.75 0.15 0.60 0.25 Outline version IEC SOT1199-1 Fig 34. Package outline SOT1199-1 (VFBGA24) ...
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... NXP Semiconductors 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 35. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA6416A Product data sheet Low-voltage translating 16-bit I maximum peak temperature = MSL limit, damage level temperature minimum peak temperature ...
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... NXP Semiconductors 18. Soldering: PCB footprints Footprint information for reflow soldering of TSSOP24 package solder land occupied area DIMENSIONS 0.650 0.750 7.200 4.500 1.350 Fig 36. PCB footprint for SOT355-1 (TSSOP24); reflow soldering PCA6416A Product data sheet Low-voltage translating 16-bit I ...
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... NXP Semiconductors Footprint information for reflow soldering of HVQFN24 package (0.105 solder land solder paste deposit solder land plus solder paste occupied area Dimensions 0.500 5.000 5.000 3.200 3.200 07-09-24 Issue date 09-06-15 Fig 37. PCB footprint for SOT994-1 (HWQFN24); reflow soldering ...
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... NXP Semiconductors 19. Abbreviations Table 25. Acronym ESD FET GPIO 2 I C-bus I/O LED LSB MSB NACK PCB POR PRR SMBus 20. Revision history Table 26. Revision history Document ID Release date PCA6416A v.2 20130110 • Modifications: Updated • Updated and “Minimum order quantity”; topside marking column is moved to • ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... PCA6416A Product data sheet Low-voltage translating 16-bit I own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. ...
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... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Voltage translation . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 Interface definition . . . . . . . . . . . . . . . . . . . . . . 7 7.3 Pointer register and command byte . . . . . . . . . 7 7.4 Register descriptions . . . . . . . . . . . . . . . . . . . . 8 7.4.1 Input port registers (00h, 01h ...