STA381BWSTR STMicroelectronics, STA381BWSTR Datasheet - Page 111
STA381BWSTR
Manufacturer Part Number
STA381BWSTR
Description
Audio DSPs Sound Terminal 2.1 High EFF Dig Audio
Manufacturer
STMicroelectronics
Datasheet
1.STA381BWSTR.pdf
(171 pages)
Specifications of STA381BWSTR
Product Category
Audio DSPs
Rohs
yes
Operating Supply Voltage
4.5 V to 25.5 V
Operating Temperature Range
0 C to + 150 C
Mounting Style
SMD/SMT
Package / Case
VQFN-48
Snr
100 dB
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STA381BWS
Note:
7.2.4
7.2.5
happens. At the same time any processing related to the I
only after the serial audio interface and the internal PLL are synchronous again.
Any mute or volume change causes some delay in the completion of the I
to the soft volume feature. The soft volume phase change must be finished before any clock
desynchronization.
Delay serial clock enable
Table 110. Delay serial clock enable
Channel input mapping
Table 111. Channel input mapping
Each channel received via I
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers map each I
Bit
Bit
5
6
7
R/W
R/W
R/W
R/W
R/W
RST
RST
0
0
1
2
S can be mapped to any internal processing channel via the
2
Doc ID 018937 Rev 6
DSCKE
S input channel to its corresponding processing channel.
Name
Name
C1IM
C2IM
Register description: Sound Terminal compatibility
0: Processing channel 1 receives left I
1: Processing channel 1 receives right I
0: Processing channel 2 receives left I
1: Processing channel 2 receives right I
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate
anomalies in some I
2
C configuration should be issued
Description
Description
2
S master devices
2
C operation due
2
2
S input
S input
2
2
S input
S input
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