C8051F560-IQR Silicon Labs, C8051F560-IQR Datasheet - Page 139

• Manufacturer Part Number: C8051F560-IQR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 32 kB 2 kB CAN2.0 LIN 2.1 SPI
• Manufacturer: Silicon Labs

Specifications of C8051F560-IQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

SFR Definition 16.1. VDM0CN: V
SFR Address = 0xFF; SFR Page = 0x00
16.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 5.4 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
16.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the value specified in Table 5.4, “Reset Electrical Characteristics,”
on page 41, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag (RST-
SRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0. Writing a 1 to the
MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of the RST pin is unaf-
fected by this reset.
Name
Reset
Bit
4:0
Type
7
6
5
Bit
VDDSTAT
VDMLVL
VDMEN
Unused
VDMEN
Name
Varies
R/W
7
VDDSTAT
V
This bit turns the V
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 16.2). Selecting the V
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V
reset source. See Table 5.4 for the minimum V
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
V
0: V
1: V
tem includes code that writes to and/or erases Flash.
Read = 00000b; Write = Don’t care.
Varies
DD
DD
DD
R
6
DD
DD
DD
DD
DD
DD
Monitor Enable.
Status.
Monitor Level Select.
Monitor Threshold is set to VRST-HIGH. This setting is required for any sys-
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
Monitor Threshold is set to VRST-LOW
VDMLVL
R/W
5
0
DD
DD
DD
monitor circuit on/off. The V
Monitor Control
monitor threshold.
Rev. 1.1
DD
R
4
0
DD
monitor threshold.
monitor as a reset source before it has stabilized
Function
R
3
0
C8051F55x/56x/57x
DD
DD
Monitor turn-on time.
R
2
0
DD
DD
Monitor cannot generate sys-
Monitor and selecting it as a
Monitor output).
R
1
0
R
0
0
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