AT89LP51ED2-20AU Atmel, AT89LP51ED2-20AU Datasheet - Page 171

• Manufacturer Part Number: AT89LP51ED2-20AU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20AU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 160

21.5
21.6
3714A–MICRO–7/11
Starting a Conversion
Noise Considerations
In ADC mode, there are no requirements on the clock frequency with respect to the system
clock. The ADC prescaler selection is independent of the system clock divider and the ADC may
operate at both higher or lower frequencies than the CPU. However, in DAC mode the ADC
clock frequency must not be higher than the CPU clock, including any clock division from the
system clock.
Figure 21-6. DADC Clock Selection
Setting the GO/BSY bit (DADC.6) when ADCE = 1 starts a single conversion in both ADC and
DAC modes. The bit remains set while the conversion is in progress and is cleared by hardware
when the conversion completes. The ADC channel should not be changed while a conversion is
in progress.
Alternatively, a conversion can be started automatically by various timer sources. Conversion
trigger sources are selected by the TRG bits in DADI. A conversion is started every time the
selected timer overflows, allowing for conversions to occur at fixed intervals. The GO/BSY bit will
be set by hardware while the conversion is in progress. Note that the timer overflow rate must be
slower than the conversion time.
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. If conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
• Keep analog signal paths as short as possible. Make sure to run analog signals tracks over
• Place the CPU in Idle during a conversion. For best results, use a Timer to start the
• If any Port 0 pins are used as digital outputs, it is essential that these do not switch while a
an analog ground plane, and keep them well away from high-speed digital tracks.
conversion while CPU is already in Idle Mode.
conversion is in progress.
INTERNAL
8MHz OSC
AT89LP51RD2/ED2/ID2 Preliminary
ACK0
ACK1
ACK2
OSC
÷ 4
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
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