AT89LP51ED2-20AU Atmel, AT89LP51ED2-20AU Datasheet - Page 5
AT89LP51ED2-20AU
Manufacturer Part Number
AT89LP51ED2-20AU
Description
8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
Manufacturer
Atmel
Datasheet
1.AT89LP51ED2-20AAU.pdf
(254 pages)
Specifications of AT89LP51ED2-20AU
Rohs
yes
Core
8051
Processor Series
AT89x
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
64 KB
Data Ram Size
256 B
On-chip Adc
Yes
Operating Supply Voltage
2.4 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TQFP-44
Mounting Style
SMD/SMT
Data Rom Size
4 KB
Interface Type
2-Wire, SPI, UART
Number Of Programmable I/os
36
Number Of Timers
3
Program Memory Type
Flash
Factory Pack Quantity
160
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Table 1-1.
3714A–MICRO–7/11
VQFP
VQFN
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Pin Number
PLCC
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Atmel AT89LP51RD2/ED2/ID2 Pin Description
PDIP
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
(1)
Symbol
GND
P4.3
P2.0
P2.1
P2.1
P2.3
P2.4
P2.5
P2.6
P2.7
P4.5
P4.4
P4.0
POL
P0.7
P0.6
P0.5
P0.4
P0.3
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Description
Ground
P4.3: User-configurable I/O Port 4bit 3.
DDA: Bidirectional Debug Data line for the On-Chip Debug Interface when OCD is enabled.
P2.0: User-configurable I/O Port 2 bit 0.
A8: External memory interface Address bit 8.
P2.1: User-configurable I/O Port 2 bit 1.
A9: External memory interface Address bit 9.
P2.2: User-configurable I/O Port 2 bit 2.
DA-: DAC negative differential output.
A10: External memory interface Address bit 10.
P2.3: User-configurable I/O Port 2 bit 3.
DA+-: DAC positive differential output.
A11: External memory interface Address bit 11.
P2.4: User-configurable I/O Port 2 bit 5.
AIN0: Analog Comparator Input 0.
A12: External memory interface Address bit 12.
P2.5: User-configurable I/O Port 2 bit 5.
AIN1: Analog Comparator Input 1.
A13: External memory interface Address bit 13.
P2.6: User-configurable I/O Port 2 bit 6.
AIN2: Analog Comparator Input 2.
A14: External memory interface Address bit 14.
P2.7: User-configurable I/O Port 2 bit 7.
AIN3: Analog Comparator Input 3.
A15: External memory interface Address bit 15.
P4.5: User-configurable I/O Port 4 bit 5.
PSEN: External memory interface Program Store Enable (active-low).
P4.4: User-configurable I/O Port 4 bit 4.
ALE: External memory interface Address Latch Enable.
P4.0: User-configurable I/O Port 4 bit 0.
SCL: TWI Serial Clock line. This line is an output in mater mode and an input in slave mode.
POL: Reset polarity
P0.7: User-configurable I/O Port 0 bit 7.
AD7: External memory interface Address/Data bit 7.
P0.6: User-configurable I/O Port 0 bit 6.
AD6: External memory interface Address/Data bit 6.
ADC6: ADC analog input 6.
P0.5: User-configurable I/O Port 0 bit 5.
AD5: External memory interface Address/Data bit 5.
ADC5: ADC analog input 5.
P0.4: User-configurable I/O Port 0 bit 4.
AD4: External memory interface Address/Data bit 4.
ADC4: ADC analog input 4.
P0.3: User-configurable I/O Port 0 bit 3.
AD3: External memory interface Address/Data bit 3.
ADC3: ADC analog input 3.
AT89LP51RD2/ED2/ID2 Preliminary
(See “External Reset” on page
55.)
5
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