STA662 STMicroelectronics, STA662 Datasheet
STA662
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STA662 Summary of contents
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... Multi-standard smart tuner module – Multi-standard car-radio receiver – Home receivers Table 1. Device summary Order code Temp range STA662 -40 °C to +85 °C TFBGA289 Doc ID 023407 Rev 1 STA662 − Data brief production data TFBGA289 2 S based on 45.6 kHz rate Package Packing ...
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... Ball out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 STA662 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Pins termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 STA662 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ARM946 subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DSP-STxP70 subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DSP-Emerald subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 IPBUS subsytem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Embedded memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SDR-SDRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hardware accelerators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Enhanced serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial link and front end interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 APB peripherals ...
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... The STA662 implements a additional SDR-SDRAM interface thus allowing to implement memory-consuming firmware like DAB middleware and DAB/FM seamless switching. To build a complete DAB/FM/AM receiver, the STA662 needs to be fed by the STA610 RF Multistandard front-end or from the STA610A RF AM/FM front-end. STA662 supports up to four RF FE connected in parallel. ...
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... Description 1.1 DAB signal processing The STA662 performs the processing of the DAB signal. It receives a complex digital signal from an DAB RF tuner either from a multi-standard RF tuner. The native sample rate is 2048 kHz. Sample rate conversion hardware is provided on-chip. This feature allows the STA662 to operate with various DAB front-ends. ...
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... DRM demodulating and decoding functional data flow diagram 1.2 FM signal processing STA662 features several strategies to improve the reception of FM signals. A DSP controlled variable bandwidth filtering of the complex base-band allows to greatly cope with adjacent channel interferences. Multipath fading distortion is mitigated by exploiting antenna switching (the antenna RF-switch is controlled through Digital pins). ...
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... DAB Radio processing requires that two DAB or Multi-standard RF tuners are connected to the STA662 single channel implementation a single RF tuner is used. In such configuration STA662 is able to demodulate at the same time both the audio and the data carried inside a single DAB ensemble. This means that the user can listen audio and receive traffic information or data broadcasted on that specific single ensemble ...
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... STA662 1.5 Overview of main functional blocks 1.5.1 STA662 architecture Figure 3. STA662 architecture diagram Doc ID 023407 Rev 1 Description 7/24 ...
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... Audio decoding The STxP70 subsystem contains a program cache to improve performance during code execution. AHB master port is used by the DSP to access the STA662 architecture while an AHB slave port is used by DMA to access xp70 subsystem memories. Debugging of the software running on the DSP-STxp70 is possible through the JTAG interface ...
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... Emerald memories are mapped on the AHB and available for the AHB masters. 1.5.7 SDR-SDRAM controller STA662 embeds an SDR-SDRAM controller. The controller is connected to the AHB multi layer architecture so that it expands the memory available for both the AHB mapped cores: ARM946 and STxP70. SDRAM controller clock is selectable by a top level register between four different possibilities: full rate, which corresponds to the ARM9 core frequency (131 ...
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... The 6-channels Stereo Channel Sample Rate Converter (SRC6) introduces flexibility to the system, since it allows exchanging data with external units whose data rate is different from the STA662 one. Signal routing to and from the STA662 is ruled by the internal audio Input/Output multiplexer (AIMUX/AOMUX) configurable by software. 1.5.10 ...
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... Serial link and front end interface The Serial Link (SLINK) and the Front End interface (FEI) blocks have been designed to connect the STA662 with different kind of tuners such as STA606 or STA610. The SLINK block performs serial to parallel conversion of data coming from the tuners while the FEI block performs decimation, filtering and other digital signal processing such as gain control, DC offset cancellation, image rejection and so on ...
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... Pin description 2 Pin description The STA662 is available in a 15x15x1.2 mm full matrix TFBGA package with 289 balls. Figure 4 indicates also basic pin functionality. 2.1 Ball out Figure 4. Ball out diagram 12/24 Doc ID 023407 Rev 1 STA662 ...
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... STA662 2.2 STA662 pin list Table 2. STA662 pin-out description Ball name Tuner interface RTC1P RTC1M CLK1P CLK1M CLK1 IQ_DATA1P IQ_DATA1M IQDATA1 RTC2P RTC2M CLK2P CLK2M CLK2 IQ_DATA2P IQ_DATA2M IQDATA2 WS2 PWR_MNG3 WAGC3 SNOOP_CTRL3 WS3P WS3M WS3 IDATA3P IDATA3M IDATA3 QDATA3P QDATA3M QDATA3 ...
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... Pin description Table 2. STA662 pin-out description (continued) Ball name CLK3 PWR_MNG4 WAGC4 SNOOP_CTRL4 WS4P WS4M WS4 IDATA4P IDATA4M IDATA4 QDATA4P QDATA4M QDATA4 CLK4P CLK4M CLK4 DBI Interface SAI_DBI_DI1 SAI_DBI_DI2 SAI_DBI_WS SAI_DBI_SCK IBOC/DRM output interface (IDO i/f) SAI_IDO1_D1 SAI_IDO1_D2 SAI_IDO1_WS SAI_IDO1_SCK SAI_IDO2_D1 SAI_IDO2_D2 ...
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... STA662 Table 2. STA662 pin-out description (continued) Ball name SSP0_RXD SSP0_TXD SSP1_FSS SSP1_CLK SSP1_RXD SSP1_TXD SSP2_FSS SSP2_CLK SSP2_RXD SSP2_TXD SSP3_FSS SSP3_CLK SSP3_RXD SSP3_TXD SSP4_FSS SSP4_CLK SSP4_RXD SSP4_TXD SDRAM interface DRAM_BANK_ADDR_1 DRAM_BANK_ADDR_0 DRAM_ADDR_12 DRAM_ADDR_11 DRAM_ADDR_10 DRAM_ADDR_9 DRAM_ADDR_8 DRAM_ADDR_7 DRAM_ADDR_6 DRAM_ADDR_5 DRAM_ADDR_4 DRAM_ADDR_3 DRAM_ADDR_2 ...
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... Pin description Table 2. STA662 pin-out description (continued) Ball name DRAM_WE_N DRAM_SEL_N_1 DRAM_SEL_N_0 DRAM_DQM_1 DRAM_DQM_0 DRAM_CKE DRAM_CAS_N DRAM_RAS_N DRAM_DATA_15 DRAM_DATA_14 DRAM_DATA_13 DRAM_DATA_12 DRAM_DATA_11 DRAM_DATA_10 DRAM_DATA_9 DRAM_DATA_8 DRAM_DATA_7 DRAM_DATA_6 DRAM_DATA_5 DRAM_DATA_4 DRAM_DATA_3 DRAM_DATA_2 DRAM_DATA_1 DRAM_DATA_0 DRAM_CLK Host Processor i/f (SDEC i/f) SDEC_SPI_CLKIN SDEC_SPI_TX SDEC_SPI_FSSIN SDEC_SPI0_EN ...
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... STA662 Table 2. STA662 pin-out description (continued) Ball name FIFOOUT_0E FIFOIN_1F FIFOOUT_2E FIFOIN_3F GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 Audio Clock Output Interface PBCLK1 PWSCLK1 PBCLK2 PWSCLK2 Audio interface AIF1_SAI1_CLK AIF1_SAI1_WS AIF1_SAI1_DIN AIF1_SAI2_CLK AIF1_SAI2_WS AIF1_SAI2_DIO AIF1_SAI3_CLK AIF1_SAI3_WS AIF1_SAI3_DIN1 AIF1_SAI3_DIN2 AIF1_SAI3_DIN3 AIF1_SAI3_DO1 AIF1_SAI3_DO2 AIF1_SAI3_DO3 ...
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... Pin description Table 2. STA662 pin-out description (continued) Ball name AIF1_SAI4_DO1 AIF1_SAI4_DO2 AIF1_SAI4_DO3 AIF1_SPDIF_IN AIF2_SAI1_CLK AIF2_SAI1_WS AIF2_SAI1_DIN AIF2_SAI2_CLK AIF2_SAI2_WS AIF2_SAI2_DIO AIF2_SAI3_CLK AIF2_SAI3_WS AIF2_SAI3_DIN1 AIF2_SAI3_DIN2 AIF2_SAI3_DIN3 AIF2_SAI3_DO1 AIF2_SAI3_DO2 AIF2_SAI3_DO3 AIF2_SAI4_CLK AIF2_SAI4_WS AIF2_SAI4_DIN1 AIF2_SAI4_DIN2 AIF2_SAI4_DIN3 AIF2_SAI4_DO1 AIF2_SAI4_DO2 AIF2_SAI4_DO3 AIF2_SPDIF_IN SCLK SDA GPIOs GPIO14 ...
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... STA662 Table 2. STA662 pin-out description (continued) Ball name GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 UARTs UART_RXD0 UART_TXD0 UART_CTS0 UART_RTS0 UART_RXD1 UART_TXD1 UART_RXD2 UART_TXD2 Debug Interface GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO13 JTAG (1) TCK (1) TDI TDO (1) TMS (1) TRST ...
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... Pin description Table 2. STA662 pin-out description (continued) Ball name Antenna switching AS0 AS1 System level signals CLKSEL0 CLKSEL1 MCLKOUT BOOTSEL0 BOOTSEL1 (1) (2) RESET_N , IOPSW0 IOPSW1 TESTSEL0 TESTSEL1 TESTSEL2 TESTSEL3 (3) DRAM_ENABLE XTAL XTI XTO AVDD2V5_OSCI30 AGNDSUB_OSCI30 AVDD1V2_OSCI30 AGND_OSCI30 2.5 Volt LDO LDO2V5 PLLs Power supply and ground signal ...
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... The DRAM_ENABLE pin must be set to logical one at PCB level. 2.3 Pins termination In order to guarantee the correct behavior of an STA662 based application it is mandatory to properly terminate unused input and inout pins. Since many of the STA662 pins have secondary/tertiary functions which depend on the specific firmware configuration strongly suggested to review the final application's schematic with ST application engineer ...
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... In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 5. TFBGA289 mechanical data and package dimensions 22/24 Doc ID 023407 Rev 1 STA662 ® ...
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... STA662 4 Revision history Table 3. Document revision history Date 06-Jul-2012 Revision 1 Initial release. Doc ID 023407 Rev 1 Revision history Changes 23/24 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 24/24 Please Read Carefully: © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 023407 Rev 1 STA662 ...