C8051F583-IQR Silicon Labs, C8051F583-IQR Datasheet - Page 191
C8051F583-IQR
Manufacturer Part Number
C8051F583-IQR
Description
8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F585-IQR.pdf
(356 pages)
Specifications of C8051F583-IQR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, P0.1 if the
ADC is configured to use the external conversion start signal (CNVSTR), P0.3 and/or P0.2 if the external
oscillator circuit is enabled, and any selected ADC or Comparator inputs. The Crossbar skips selected pins
as if they were already assigned, and moves to the next unassigned pin.
Registers XBR0, XBR1, XBR2, and XBR3 are used to assign the digital I/O resources to the physical I/O
Port pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the
SMBus (SDA and SCL); and similarly when the UART, CAN or LIN are selected, the Crossbar assigns both
pins associated with the peripheral (TX and RX).
Port
Special
Function
Signals
PIN I/O
UART0_TX
UART0_RX
CAN_TX
CAN_RX
SCK
MISO
MOSI
NSS
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
LIN_TX
LIN_RX
UART1_TX
UART1_RX
CP2
CP2A
CEX6
CEX7
CEX8
CEX9
CEX10
CEX11
ECI1
T4
T4EX
T5
T5EX
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Figure 20.3. Peripheral Availability on Port I/O Pins
P0
P1
Rev. 1.2
P2
available on the 48-pin
P3.1-P3.7, P4.0 only
and 40-pin packages
C8051F58x/F59x
P3
available on the 48-
P4.1-P4.7 only
pin packages
P4
191
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