C8051F583-IQR Silicon Labs, C8051F583-IQR Datasheet - Page 327
C8051F583-IQR
Manufacturer Part Number
C8051F583-IQR
Description
8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F585-IQR.pdf
(356 pages)
Specifications of C8051F583-IQR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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SFR Definition 28.3. PCA0PWM: PCA0 PWM Configuration
SFR Address = 0xD9; SFR Page = 0x0F
Name
Reset
Bit
4:2
1:0 CLSEL[1:0] Cycle Length Select.
Type
7
6
5
Bit
Unused
ARSEL
ECOV
Name
COVF
ARSEL
R/W
7
0
Auto-Reload Register Select.
This bit selects whether to read and write the normal PCA0 capture/compare registers
(PCA0CPn), or the Auto-Reload registers at the same SFR addresses. This function
is used to define the reload value for 9, 10, and 11-bit PWM modes. In all other
modes, the Auto-Reload registers have no function.
0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn.
1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn.
Cycle Overflow Interrupt Enable.
This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt.
0: COVF will not generate PCA0 interrupts.
1: A PCA0 interrupt will be generated when COVF is set.
Cycle Overflow Flag.
This bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main PCA0 coun-
ter (PCA0). The specific bit used for this flag depends on the setting of the Cycle
Length Select bits. The bit can be set by hardware or software, but must be cleared by
software.
0: No overflow has occurred since the last time this bit was cleared.
1: An overflow has occurred since the last time this bit was cleared.
Read = 000b; Write = Don’t care.
When 16-bit PWM mode is not selected, these bits select the length of the PWM
cycle, between 8, 9, 10, or 11 bits. This affects all channels configured for PWM which
are not using 16-bit PWM mode. These bits are ignored for individual channels config-
ured to16-bit PWM mode.
00: 8 bits.
01: 9 bits.
10: 10 bits.
11: 11 bits.
ECOV
R/W
6
0
COVF
R/W
5
0
Rev. 1.2
R
4
0
Function
R
3
0
C8051F58x/F59x
R
2
0
1
0
CLSEL[1:0]
R/W
0
0
327
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