C8051T326-GMR Silicon Labs, C8051T326-GMR Datasheet - Page 118
![no-image](/images/no-image-200.jpg)
C8051T326-GMR
Manufacturer Part Number
C8051T326-GMR
Description
8-bit Microcontrollers - MCU USB-OTP-16K-QFN28
Manufacturer
Silicon Labs
Datasheet
1.C8051T322-GQR.pdf
(292 pages)
Specifications of C8051T326-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051T620/621/320/321/322/323
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V
V
Important Note: If the V
is selected as a reset source. Selecting the V
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V
state is shown below:
1. Enable the V
2. If necessary, wait for the V
3. Select the V
See Figure 20.2 for V
monitor reset. See Table 7.4 for complete electrical characteristics of the V
118
DD
monitor will still be disabled after the reset.
DD
DD
monitor as a reset source (PORSF bit in RSTSRC = 1).
monitor (VDMEN bit in VDM0CN = 1).
DD
DD
monitor timing; note that the power-on-reset delay is not incurred after a V
monitor is being turned on from a disabled state, it should be enabled before it
DD
monitor to stabilize (see Table 7.4 for the V
DD
monitor is disabled by code and a software reset is performed, the
DD
monitor and configuring it as a reset source from a disabled
DD
Rev. 1.1
monitor as a reset source before it is enabled and stabi-
DD
DD
monitor.
Monitor turn-on time).
DD
DD
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