C8051F566-IQR Silicon Labs, C8051F566-IQR Datasheet - Page 155

• Manufacturer Part Number: C8051F566-IQR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB LIN 2.1 SPI
• Manufacturer: Silicon Labs

Specifications of C8051F566-IQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

18. Oscillators and Clock Selection
C8051F55x/56x/57x devices include a programmable internal high-frequency oscillator, an external oscil-
lator drive circuit, and a clock multiplier. The internal oscillator can be enabled/disabled and calibrated
using the OSCICN, OSCICRS, and OSCIFIN registers, as shown in Figure 18.1. The system clock can be
sourced by the external oscillator circuit or the internal oscillator. The clock multiplier can produce three
possible base outputs which can be scaled by a programmable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or
1/3), or 2/7: Internal Oscillator x 2, Internal Oscillator x 4, External Oscillator x 2, or External Oscillator x 4.
18.1. System Clock Selection
The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock.
CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the exter-
nal oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the
system clock. The system clock may be switched on-the-fly between the internal oscillator, external oscilla-
tor, and Clock Multiplier so long as the selected clock source is enabled and has settled.
The internal oscillator requires little start-up time and may be selected as the system clock immediately fol-
lowing the register write which enables the oscillator. The external RC and C modes also typically require
no startup time.
External crystals and ceramic resonators however, typically require a start-up time before they are settled
and ready for use. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to 1 by hardware when the
external crystal or ceramic resonator is settled. In crystal mode, to avoid reading a false XTLVLD, soft-
ware should delay at least 1 ms between enabling the external oscillator and checking XTLVLD.
VDD
Option 2
Option 3
XTAL2
XTAL2
Option 1
Option 4
XTAL2
10M
XTAL1
XTAL2
Figure 18.1. Oscillator Options
OSCICRS
Programmable Internal
Circuit
Rev. 1.1
Input
CAL
Clock Generator
OSCXCN
OSCIFIN
EXOSC / 2
EXTOSC
IOSC / 2
OSC
IOSC
EN
EXOSC
C8051F55x/56x/57x
OSCICN
CLOCK MULTIPLIER
IOSC
x4
CLKMUL
n
n
CLKSEL
SYSCLK
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