C8051F566-IQR Silicon Labs, C8051F566-IQR Datasheet - Page 93

• Manufacturer Part Number: C8051F566-IQR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB LIN 2.1 SPI
• Manufacturer: Silicon Labs

Specifications of C8051F566-IQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

11.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F55x/56x/57x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but
can be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always used
to read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash access
feature provides a mechanism for the C8051F55x/56x/57x to update program code and use the program
memory space for non-volatile data storage. Refer to Section “14. Flash Memory” on page 124 for further
details.
11.2. Data Memory
The C8051F55x/56x/57x devices include 2304 bytes of RAM data memory. 256 bytes of this memory is
mapped into the internal RAM space of the 8051. The other 2048 bytes of this memory is on-chip “exter-
nal” memory. The data memory map is shown in Figure 11.1 for reference.
11.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
Flash Memory Space
(32 kB Flash Device)
C8051F550/1/2/3
C8051F560/1/2/3/8/9
C8051F570/1
Lock Byte Page
Reserved Area
Lock Byte
Figure 11.2. Flash Program Memory Map
0x7FFF
0x7C00
0x7BFF
0x7BFE
0x7A00
0x0000
Rev. 1.1
Flash Memory Space
(16 kB Flash Device)
C8051F554/5/6/7
C8051F564/5/6/7
C8051F572/3/4/5
Lock Byte Page
Lock Byte
C8051F55x/56x/57x
0x3FFF
0x3FFE
0x3E00
0x0000
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